////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.01
//  \   \         Filename: kcuart_rx.v
//  /   /         Date Last Modified:  08/04/2004
// /___/   /\     Date Created: 10/16/2002
// \   \  /  \
//  \___\/\___\
//
//Device:  	Xilinx
//Purpose: 	
// 	Constant (K) Compact UART Receiver
//Reference:
// 	None
//Revision History:
//    Rev 1.00 - kc - Start of design entry in VHDL,  10/16/2002.
//    Rev 1.01 - sus - Converted to verilog,  08/04/2004.
//    Rev 1.02 - njs - Synplicity attributes added,  09/06/2004.
//    Rev 1.03 - njs - defparam values corrected,  12/01/2005.
//////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail  picoblaze@xilinx.com
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer: 
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the 
// essential purpose of any limited remedies herein. 
//////////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1ps

module kcuart_rx
     (serial_in,
      data_out,
      data_strobe,
      en_16_x_baud,
      clk);

input 		serial_in;
output [7:0] 	data_out;
output 		data_strobe;
input 		en_16_x_baud;
input 		clk;

////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCUART_RX
//	 
//
////////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////////
//
// wires used in KCUART_RX
//
////////////////////////////////////////////////////////////////////////////////////
//
wire 		sync_serial        ;
wire 		stop_bit           ;
wire 	[7:0] 	data_int     ;
wire 	[7:0] 	data_delay   ;
wire 		start_delay        ;
wire 		start_bit          ;
wire 		edge_delay         ;
wire 		start_edge         ;
wire 		decode_valid_char  ;
wire 		valid_char         ;
wire 		decode_purge       ;
wire 		purge              ;
wire 	[8:0] 	valid_srl_delay   ;
wire 	[8:0] 	valid_reg_delay   ;
wire 		decode_data_strobe ;
//
//
////////////////////////////////////////////////////////////////////////////////////
//
// Attributes to define LUT contents during implementation 
// The information is repeated in the defparam for functional simulation
//
////////////////////////////////////////////////////////////////////////////////////

// synthesis attribute init of start_srl is "0000"; 
// synthesis attribute init of edge_srl is "0000"; 
// synthesis attribute init of valid_lut is "0040"; 
// synthesis attribute init of purge_lut is "54"; 
// synthesis attribute init of strobe_lut is "8"; 
// synthesis attribute init of delay15_srl_7 is "0000"; 
// synthesis attribute init of delay15_srl_6 is "0000"; 
// synthesis attribute init of delay15_srl_5 is "0000"; 
// synthesis attribute init of delay15_srl_4 is "0000"; 
// synthesis attribute init of delay15_srl_3 is "0000"; 
// synthesis attribute init of delay15_srl_2 is "0000"; 
// synthesis attribute init of delay15_srl_1 is "0000"; 
// synthesis attribute init of delay15_srl_0 is "0000"; 
// synthesis attribute init of valid_delay15_srl_0 is "0000"; 
// synthesis attribute init of valid_delay16_srl_1 is "0000"; 
// synthesis attribute init of valid_delay16_srl_2 is "0000"; 
// synthesis attribute init of valid_delay16_srl_3 is "0000"; 
// synthesis attribute init of valid_delay16_srl_4 is "0000"; 
// synthesis attribute init of valid_delay16_srl_5 is "0000"; 
// synthesis attribute init of valid_delay16_srl_6 is "0000"; 
// synthesis attribute init of valid_delay16_srl_7 is "0000"; 
// synthesis attribute init of valid_delay16_srl_8 is "0000"; 

//
////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCUART_RX circuit description
//
////////////////////////////////////////////////////////////////////////////////////
//	

  // Synchronise input serial data to system clock

FD sync_reg
( 	.D(serial_in),
      .Q(sync_serial),
      .C(clk) );

FD stop_reg
( 	.D(sync_serial),
      .Q(stop_bit),
      .C(clk) );


// Data delays to capture data at 16 time baud rate
// Each SRL16E is followed by a flip-flop for best timing

	SRL16E delay15_srl_0
	(  	.D(data_int[1]),
	      .CE(en_16_x_baud),
      	.CLK(clk),
	      .A0(1'b0),
	      .A1(1'b1),
	      .A2(1'b1),
	      .A3(1'b1),
	      .Q(data_delay[0] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_0.INIT = 16'h0000;
	// synthesis translate_on

       SRL16E delay15_srl_1
       (   	.D(data_int[2]),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[1] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_1.INIT = 16'h0000;
	// synthesis translate_on

      SRL16E delay15_srl_2
      (   	.D(data_int[3]),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[2] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_2.INIT = 16'h0000;
	// synthesis translate_on

      SRL16E delay15_srl_3
      (   	.D(data_int[4]),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[3] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_3.INIT = 16'h0000;
	// synthesis translate_on

      SRL16E delay15_srl_4
      (   	.D(data_int[5]),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[4] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_4.INIT = 16'h0000;
	// synthesis translate_on

      SRL16E delay15_srl_5
      (   	.D(data_int[6]),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[5] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_5.INIT = 16'h0000;
	// synthesis translate_on

      SRL16E delay15_srl_6
      (   	.D(data_int[7]),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[6] ))/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_6.INIT = 16'h0000;
	// synthesis translate_on
      
	SRL16E  delay15_srl_7
      (   	.D(stop_bit),
            .CE(en_16_x_baud),
            .CLK(clk),
            .A0(1'b0),
            .A1(1'b1),
            .A2(1'b1),
            .A3(1'b1),
            .Q(data_delay[7]) )/* synthesis xc_props = "INIT=0000"*/;
	// synthesis translate_off
	defparam delay15_srl_7.INIT = 16'h0000;
	// synthesis translate_on

	FDE data_reg_0
      ( 	.D(data_delay[0]),
            .Q(data_int[0]),
            .CE(en_16_x_baud),
            .C(clk) );

	FDE data_reg_1
      ( 	.D(data_delay[1]),
		.Q(data_int[1]),
            .CE(en_16_x_baud),
            .C(clk) );

	FDE data_reg_2
      ( 	.D(data_delay[2]),
            .Q(data_int[2]),
            .CE(en_16_x_baud),
            .C(clk) );

	FDE data_reg_3
      ( 	.D(data_delay[3]),
            .Q(data_int[3]),
            .CE(en_16_x_baud),
            .C(clk) );

	FDE data_reg_4
      ( 	.D(data_delay[4]),
            .Q(data_int[4]),
            .CE(en_16_x_baud),
            .C(clk) );

	FDE data_reg_5
      ( 	.D(data_delay[5]),
            .Q(data_int[5]),
            .CE(en_16_x_baud),
            .C(clk) );

	FDE data_reg_6