C:/Xilinx/ISE81/verilog/src/glbl.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/kcuart_rx.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/uart_rx.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/bbfifo_16x8.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/SRL16E.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/MULT_AND.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FDRS.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/MUXF6.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/kcuart_tx.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/uart_tx.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/DCM.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/IBUFG.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/BUFG.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/my_dcm.v
L:/IP_I.19/rtf/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V1_1.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/program.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/RAM32X1S.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/MUXF5.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/RAM64X1S.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/RAM16X1D.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FDRSE.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/INV.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/XORCY.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/MUXCY.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/LUT2.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FDRE.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/LUT3.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FDE.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FD.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/LUT4.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FDS.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/FDR.v
//fasban/embedded/I.27/rtf/verilog/src/unisims/LUT1.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/kcpsm3.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/loopback.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/testbench.v