HSPICE model for the Micron 256Mb DDR2 SDRAM - Die Revision "B"

REV 2.0:  August 1, 2003.
  This version contains 6 different models:
    - rdqsbuff.inc is the output model for RDQS.
    - dmbuff.inc is the input model for DM.
    - dqbuff.inc is the DQ I/O model.
    - dqsbuff.inc is the differential DQS I/O model.
    - inbuff.inc is the input model for all inputs except for DM and CLK/CLK#.
    - clkbuff.inc is the input model for CLK and CLK#.
    - all models match latest silicon measurements

REV 2.1:  November 4, 2003.
    - re-encrypted dqsbuff.inc file to fix HSPICE encryption error causing 
      DQS simulation to fail

REV 2.2:  May 16, 2005.
    - Updated DQ and RDQS models reflect new drive strength trimming
      (less min/max I-V curve variation), reduce input capacitance,
      and 50 ohm ODT capability
    - Typical temperature changed from 25C to 40C
    - all models updated with latest transistor models.
    - all models updated with parasitic netlists to better match real silicon

REV 2.3:  November 2, 2005.
    - all models updated with new naming convention

Rev 2.4:  April 11, 2006.
    - .inc files updated to use the same encrypted netlists for 400/533 and
      667/800 models.
    - model.cnr file updated to work with new .inc files

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                Copyright 2003 Micron Technology, Inc. All rights reserved.