Analysis & Synthesis report for RESERV
Sat Sep 17 10:15:28 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (No Restructuring Performed)
  5. WYSIWYG Cells
  6. General Register Statistics
  7. SignalTap II Logic Analyzer Settings
  8. In-System Memory Content Editor Setting
  9. Hierarchy
 10. Analysis & Synthesis Resource Utilization by Entity
 11. Analysis & Synthesis Equations
 12. Analysis & Synthesis Source Files Read
 13. Analysis & Synthesis Resource Usage Summary
 14. Analysis & Synthesis RAM Summary
 15. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Sep 17 10:15:27 2005    ;
; Quartus II Version          ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name               ; RESERV                                   ;
; Top-level Entity Name       ; RESERV                                   ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 553                                      ;
; Total pins                  ; 36                                       ;
; Total memory bits           ; 45,056                                   ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C8  ;               ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;