--lpm_counter DEVICE_FAMILY="Cyclone" lpm_modulus=18 lpm_width=5 aclr clk_en(vcc) clock q
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_counter 2004:04:21:01:21:20:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ  VERSION_END


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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 10 
SUBDESIGN cntr_gv7
( 
	aclr	:	input;
	clk_en	:	input;
	clock	:	input;
	q[4..0]	:	output;
) 
VARIABLE
	cmpr1_aeb_int	:	WIRE;
	cmpr1_aeb	:	WIRE;
	cmpr1_dataa[4..0]	:	WIRE;
	cmpr1_datab[4..0]	:	WIRE;
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "11AA",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella4 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	cout_bit : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "F8F8",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "off"
		);
	a_val[4..0]	: WIRE;
	aclr_actual	: WIRE;
	aset_node	: WIRE;
	compare_result	: WIRE;
	data[4..0]	: NODE;
	modulus_bus[4..0]	: WIRE;
	modulus_trigger	: WIRE;
	s_val[4..0]	: WIRE;
	safe_q[4..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;
	sset_node	: WIRE;
	time_to_clear	: WIRE;
	updownDir	: WIRE;

BEGIN 
	IF (cmpr1_dataa[] == cmpr1_datab[]) THEN
		cmpr1_aeb_int = VCC;
	ELSE
		cmpr1_aeb_int = GND;
	END IF;
	cmpr1_aeb = cmpr1_aeb_int;
	cmpr1_dataa[] = safe_q[];
	cmpr1_datab[] = modulus_bus[];
	counter_cella[4..0].aclr = aclr_actual;
	counter_cella[4..0].aload = B"00000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[4].cin = counter_cella[3].cout;
	counter_cella[4..0].clk = clock;
	counter_cella[4..0].dataa = safe_q[];
	counter_cella[4..0].datab = B"00000";
	counter_cella[4..0].datac = ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updownDir)));
	counter_cella[4..0].ena = clk_en;
	counter_cella[4..0].sclr = sclr;
	counter_cella[4..0].sload = (sload # modulus_trigger);
	cout_bit.cin = counter_cella[4].cout;
	cout_bit.dataa = updownDir;
	cout_bit.datab = time_to_clear;
	a_val[] = B"11111";
	aclr_actual = aclr;
	aset_node = B"0";
	compare_result = cmpr1_aeb;
	data[] = GND;
	modulus_bus[] = B"10001";
	modulus_trigger = cout_bit.combout;
	q[] = safe_q[];
	s_val[] = B"11111";
	safe_q[] = counter_cella[4..0].regout;
	sclr = GND;
	sload = GND;
	sset_node = B"0";
	time_to_clear = compare_result;
	updownDir = B"1";
END;
--VALID FILE