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--D1_q_a[7] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[7]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = clkadr;
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[7] = D1_q_a[7]_PORT_A_data_out[0];


--D1_q_a[6] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[6]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[6]_PORT_A_address_reg = DFFE(D1_q_a[6]_PORT_A_address, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_clock_0 = clkadr;
D1_q_a[6]_PORT_A_data_out = MEMORY(, , D1_q_a[6]_PORT_A_address_reg, , , , , , D1_q_a[6]_clock_0, , , , , );
D1_q_a[6] = D1_q_a[6]_PORT_A_data_out[0];


--D1_q_a[5] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[5]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[5]_PORT_A_address_reg = DFFE(D1_q_a[5]_PORT_A_address, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_clock_0 = clkadr;
D1_q_a[5]_PORT_A_data_out = MEMORY(, , D1_q_a[5]_PORT_A_address_reg, , , , , , D1_q_a[5]_clock_0, , , , , );
D1_q_a[5] = D1_q_a[5]_PORT_A_data_out[0];


--D1_q_a[4] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[4]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[4]_PORT_A_address_reg = DFFE(D1_q_a[4]_PORT_A_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_clock_0 = clkadr;
D1_q_a[4]_PORT_A_data_out = MEMORY(, , D1_q_a[4]_PORT_A_address_reg, , , , , , D1_q_a[4]_clock_0, , , , , );
D1_q_a[4] = D1_q_a[4]_PORT_A_data_out[0];


--D1_q_a[3] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[3]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[3]_PORT_A_address_reg = DFFE(D1_q_a[3]_PORT_A_address, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_clock_0 = clkadr;
D1_q_a[3]_PORT_A_data_out = MEMORY(, , D1_q_a[3]_PORT_A_address_reg, , , , , , D1_q_a[3]_clock_0, , , , , );
D1_q_a[3] = D1_q_a[3]_PORT_A_data_out[0];


--D1_q_a[2] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[2]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = clkadr;
D1_q_a[2]_PORT_A_data_out = MEMORY(, , D1_q_a[2]_PORT_A_address_reg, , , , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2] = D1_q_a[2]_PORT_A_data_out[0];


--D1_q_a[1] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[1]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = clkadr;
D1_q_a[1]_PORT_A_data_out = MEMORY(, , D1_q_a[1]_PORT_A_address_reg, , , , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1] = D1_q_a[1]_PORT_A_data_out[0];


--D1_q_a[0] is pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[0]_PORT_A_address = BUS(adr[0], adr[1], adr[2], adr[3], adr[4], adr[5], adr[6]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = clkadr;
D1_q_a[0]_PORT_A_data_out = MEMORY(, , D1_q_a[0]_PORT_A_address_reg, , , , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out[0];


--clkadr is clkadr
--operation mode is input

clkadr = INPUT();


--adr[0] is adr[0]
--operation mode is input

adr[0] = INPUT();


--adr[1] is adr[1]
--operation mode is input

adr[1] = INPUT();


--adr[2] is adr[2]
--operation mode is input

adr[2] = INPUT();


--adr[3] is adr[3]
--operation mode is input

adr[3] = INPUT();


--adr[4] is adr[4]
--operation mode is input

adr[4] = INPUT();


--adr[5] is adr[5]
--operation mode is input

adr[5] = INPUT();


--adr[6] is adr[6]
--operation mode is input

adr[6] = INPUT();


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(D1_q_a[7]);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(D1_q_a[6]);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(D1_q_a[5]);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(D1_q_a[4]);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(D1_q_a[3]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(D1_q_a[2]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(D1_q_a[1]);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(D1_q_a[0]);