|lcdmddr
lcden <= lcdmpddr:inst.en
sclk => lcdmpddr:inst.sclk
sclk => pprom6x8:inst2.clock
start => lcdmpddr:inst.start
clear => lcdmpddr:inst.clear
sel[0] => lcdmpddr:inst.sel[0]
sel[1] => lcdmpddr:inst.sel[1]
lcdr/w <= lcdmpddr:inst.r_w
lcdd/i <= lcdmpddr:inst.d_i
lcdd[0] <= lcdmpddr:inst.db[0]
lcdd[1] <= lcdmpddr:inst.db[1]
lcdd[2] <= lcdmpddr:inst.db[2]
lcdd[3] <= lcdmpddr:inst.db[3]
lcdd[4] <= lcdmpddr:inst.db[4]
lcdd[5] <= lcdmpddr:inst.db[5]
lcdd[6] <= lcdmpddr:inst.db[6]
lcdd[7] <= lcdmpddr:inst.db[7]


|lcdmddr|lcdmpddr:inst
sclk => scount[25].CLK
sclk => scount[24].CLK
sclk => scount[23].CLK
sclk => scount[22].CLK
sclk => scount[21].CLK
sclk => scount[20].CLK
sclk => scount[19].CLK
sclk => scount[18].CLK
sclk => scount[17].CLK
sclk => scount[16].CLK
sclk => scount[15].CLK
sclk => scount[14].CLK
sclk => scount[13].CLK
sclk => scount[12].CLK
sclk => scount[11].CLK
sclk => scount[10].CLK
sclk => scount[9].CLK
sclk => scount[8].CLK
sclk => scount[7].CLK
sclk => scount[6].CLK
sclk => scount[5].CLK
sclk => scount[4].CLK
sclk => scount[3].CLK
sclk => scount[2].CLK
sclk => scount[1].CLK
sclk => scount[0].CLK
sclk => scount[26].CLK
start => i179.IN1
clear => i5.OUTPUTSELECT
clear => i6.OUTPUTSELECT
clear => i7.OUTPUTSELECT
clear => i8.OUTPUTSELECT
clear => i9.OUTPUTSELECT
clear => i10.OUTPUTSELECT
clear => i11.OUTPUTSELECT
clear => i12.OUTPUTSELECT
clear => i13.OUTPUTSELECT
clear => i14.OUTPUTSELECT
clear => i15.OUTPUTSELECT
clear => i16.OUTPUTSELECT
clear => i17.OUTPUTSELECT
clear => i18.OUTPUTSELECT
clear => i19.OUTPUTSELECT
clear => i20.OUTPUTSELECT
clear => i21.OUTPUTSELECT
clear => i22.OUTPUTSELECT
clear => i23.OUTPUTSELECT
clear => i24.OUTPUTSELECT
clear => i25.OUTPUTSELECT
clear => i26.OUTPUTSELECT
clear => i27.OUTPUTSELECT
clear => i28.OUTPUTSELECT
clear => i29.OUTPUTSELECT
clear => i30.OUTPUTSELECT
clear => i31.OUTPUTSELECT
clear => i161.OUTPUTSELECT
clear => i162.OUTPUTSELECT
clear => i163.OUTPUTSELECT
clear => i164.OUTPUTSELECT
clear => i165.OUTPUTSELECT
clear => i166.OUTPUTSELECT
clear => i167.OUTPUTSELECT
clear => i168.OUTPUTSELECT
clear => i169.OUTPUTSELECT
clear => i180.IN0
clear => i202.OUTPUTSELECT
clear => i203.OUTPUTSELECT
clear => i204.OUTPUTSELECT
clear => i205.OUTPUTSELECT
clear => i209.OUTPUTSELECT
clear => i210.OUTPUTSELECT
clear => dbnc.ENA
clear => r_w~reg0.ENA
clear => en~reg0.ENA
prom_data[0] => i~22.IN10
prom_data[1] => i~21.IN10
prom_data[2] => i~20.IN10
prom_data[3] => i~19.IN10
prom_data[4] => i~18.IN10
prom_data[5] => i~17.IN10
prom_data[6] => i~16.IN10
prom_data[7] => i~15.IN10
prom_data[8] => i226.IN1
sel[0] => clkm.IN1
sel[1] => clkm.IN0
en <= en~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_w <= r_w~reg0.DB_MAX_OUTPUT_PORT_TYPE
d_i <= d_i~reg0.DB_MAX_OUTPUT_PORT_TYPE
promadr[0] <= i108.DB_MAX_OUTPUT_PORT_TYPE
promadr[1] <= i107.DB_MAX_OUTPUT_PORT_TYPE
promadr[2] <= i106.DB_MAX_OUTPUT_PORT_TYPE
promadr[3] <= i105.DB_MAX_OUTPUT_PORT_TYPE
promadr[4] <= i104.DB_MAX_OUTPUT_PORT_TYPE
promadr[5] <= i103.DB_MAX_OUTPUT_PORT_TYPE
promadr[6] <= i102.DB_MAX_OUTPUT_PORT_TYPE
promadr[7] <= i101.DB_MAX_OUTPUT_PORT_TYPE
db[0] <= db[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[1] <= db[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[2] <= db[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[3] <= db[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[4] <= db[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[5] <= db[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[6] <= db[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[7] <= db[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcdmddr|pprom6x8:inst2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]


|lcdmddr|pprom6x8:inst2|altsyncram:altsyncram_component
address_a[0] => altsyncram_8ck:auto_generated.address_a[0]
address_a[1] => altsyncram_8ck:auto_generated.address_a[1]
address_a[2] => altsyncram_8ck:auto_generated.address_a[2]
address_a[3] => altsyncram_8ck:auto_generated.address_a[3]
address_a[4] => altsyncram_8ck:auto_generated.address_a[4]
address_a[5] => altsyncram_8ck:auto_generated.address_a[5]
address_a[6] => altsyncram_8ck:auto_generated.address_a[6]
address_a[7] => altsyncram_8ck:auto_generated.address_a[7]
clock0 => altsyncram_8ck:auto_generated.clock0
q_a[0] <= altsyncram_8ck:auto_generated.q_a[0]
q_a[1] <= altsyncram_8ck:auto_generated.q_a[1]
q_a[2] <= altsyncram_8ck:auto_generated.q_a[2]
q_a[3] <= altsyncram_8ck:auto_generated.q_a[3]
q_a[4] <= altsyncram_8ck:auto_generated.q_a[4]
q_a[5] <= altsyncram_8ck:auto_generated.q_a[5]
q_a[6] <= altsyncram_8ck:auto_generated.q_a[6]
q_a[7] <= altsyncram_8ck:auto_generated.q_a[7]
q_a[8] <= altsyncram_8ck:auto_generated.q_a[8]
q_b[0] <= <UNC>


|lcdmddr|pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_8ck:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT