{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 13 14:21:31 2006 " "Info: Processing started: Thu Jul 13 14:21:31 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off lcdmddr -c lcdmddr " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off lcdmddr -c lcdmddr" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "lcdmddr EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design lcdmddr" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sclk Global clock in PIN 28 " "Info: Automatically promoted signal sclk to use Global clock in PIN 28" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmddr.bdf" "" "" { Schematic "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmddr.bdf" { { 48 -8 160 64 "sclk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcdmpddr:inst\|lpm_counter:scount_rtl_1\|cntr_lc7:auto_generated\|safe_q\[15\] Global clock " "Info: Automatically promoted some destinations of signal lcdmpddr:inst\|lpm_counter:scount_rtl_1\|cntr_lc7:auto_generated\|safe_q\[15\] to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcdmpddr:inst\|lpm_counter:scount_rtl_1\|cntr_lc7:auto_generated\|counter_cella15 " "Info: Destination lcdmpddr:inst\|lpm_counter:scount_rtl_1\|cntr_lc7:auto_generated\|counter_cella15 may be non-global or may not use global clock" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/cntr_lc7.tdf" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/cntr_lc7.tdf" 261 8 0 } }  } 0}  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/cntr_lc7.tdf" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/cntr_lc7.tdf" 261 8 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcdmpddr:inst\|clkm~1 Global clock " "Info: Automatically promoted some destinations of signal lcdmpddr:inst\|clkm~1 to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcdmpddr:inst\|dbnc " "Info: Destination lcdmpddr:inst\|dbnc may be non-global or may not use global clock" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 74 -1 0 } }  } 0}  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 24 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.024 ns register memory " "Info: Estimated most critical path is register to memory delay of 4.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcdmpddr:inst\|lpm_counter:cntm_rtl_0\|cntr_sv7:auto_generated\|safe_q\[4\] 1 REG LAB_X31_Y9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y9; Fanout = 5; REG Node = 'lcdmpddr:inst\|lpm_counter:cntm_rtl_0\|cntr_sv7:auto_generated\|safe_q\[4\]'" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "" { lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/cntr_sv7.tdf" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/cntr_sv7.tdf" 118 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 0.653 ns lcdmpddr:inst\|process2~193 2 COMB LAB_X31_Y9 2 " "Info: 2: + IC(0.211 ns) + CELL(0.442 ns) = 0.653 ns; Loc. = LAB_X31_Y9; Fanout = 2; COMB Node = 'lcdmpddr:inst\|process2~193'" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "0.653 ns" { lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4] lcdmpddr:inst|process2~193 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.611 ns) + CELL(0.590 ns) 1.854 ns lcdmpddr:inst\|process2~194 3 COMB LAB_X35_Y9 1 " "Info: 3: + IC(0.611 ns) + CELL(0.590 ns) = 1.854 ns; Loc. = LAB_X35_Y9; Fanout = 1; COMB Node = 'lcdmpddr:inst\|process2~194'" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "1.201 ns" { lcdmpddr:inst|process2~193 lcdmpddr:inst|process2~194 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(-0.013 ns) + CELL(0.590 ns) 2.431 ns lcdmpddr:inst\|process2~195 4 COMB LAB_X35_Y9 7 " "Info: 4: + IC(-0.013 ns) + CELL(0.590 ns) = 2.431 ns; Loc. = LAB_X35_Y9; Fanout = 7; COMB Node = 'lcdmpddr:inst\|process2~195'" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "0.577 ns" { lcdmpddr:inst|process2~194 lcdmpddr:inst|process2~195 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.292 ns) 3.008 ns lcdmpddr:inst\|promadr\[0\]~24 5 COMB LAB_X35_Y9 9 " "Info: 5: + IC(0.285 ns) + CELL(0.292 ns) = 3.008 ns; Loc. = LAB_X35_Y9; Fanout = 9; COMB Node = 'lcdmpddr:inst\|promadr\[0\]~24'" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "0.577 ns" { lcdmpddr:inst|process2~195 lcdmpddr:inst|promadr[0]~24 } "NODE_NAME" } } } { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.383 ns) 4.024 ns pprom6x8:inst2\|altsyncram:altsyncram_component\|altsyncram_gkq:auto_generated\|ram_block1a8~porta_address_reg0 6 MEM M4K_X33_Y9 1 " "Info: 6: + IC(0.633 ns) + CELL(0.383 ns) = 4.024 ns; Loc. = M4K_X33_Y9; Fanout = 1; MEM Node = 'pprom6x8:inst2\|altsyncram:altsyncram_component\|altsyncram_gkq:auto_generated\|ram_block1a8~porta_address_reg0'" {  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "1.016 ns" { lcdmpddr:inst|promadr[0]~24 pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } } { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/altsyncram_gkq.tdf" "" "" { Text "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C6/08 lcdmddr/db/altsyncram_gkq.tdf" 190 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.297 ns 57.08 % " "Info: Total cell delay = 2.297 ns ( 57.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.727 ns 42.92 % " "Info: Total interconnect delay = 1.727 ns ( 42.92 % )" {  } {  } 0}  } { { "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/實驗程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "4.024 ns" { lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4] lcdmpddr:inst|process2~193 lcdmpddr:inst|process2~194 lcdmpddr:inst|process2~195 lcdmpddr:inst|promadr[0]~24 pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "2 " "Info: Fitter placement operations ending: elapsed time = 2 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "5 " "Info: Fitter routing operations ending: elapsed time = 5 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 14:21:52 2006 " "Info: Processing ended: Thu Jul 13 14:21:52 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0}  } {  } 0}