+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C12Q240C8       ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; Off                ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                   ; To                                                                                                           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 6.113 ns                                       ; clear                                                                  ; lcdmpddr:inst|stks[3]                                                                                        ;            ; sclk     ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.687 ns                                      ; lcdmpddr:inst|en                                                       ; lcden                                                                                                        ; sclk       ;          ; 0            ;
; Clock Setup: 'sclk'          ; N/A   ; None          ; 88.54 MHz ( period = 11.294 ns )               ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5] ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg4 ; sclk       ; sclk     ; 0            ;
; Clock Setup: 'sel[0]'        ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5]                                       ; sel[0]     ; sel[0]   ; 0            ;
; Clock Setup: 'sel[1]'        ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5]                                       ; sel[1]     ; sel[1]   ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                        ;                                                                                                              ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; sclk            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sel[1]          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sel[0]          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;