//-----------------------------------------------------------------
// ycrcb2rgb_wire_mult.v - Color Space Converter
//                         Virtex-II Video Demo Board
//
//
//
//
//                  Author: Gregg C. Hawkes
//                  Senior Staff Applications Engineer
//
//                  Video Applications
//                  Advanced Products Division
//                  Xilinx, Inc.
//
//                  Copyright (c) 1999 Xilinx, Inc.
//                  All rights reserved
//
//                  Date:   Aug. 6, 2001
//                  For:    Video Demo Board
//
//                  RESTRICTED RIGHTS LEGEND
//
//      This software has not been published by the author, and 
//      has been disclosed to others for the purpose of enhancing 
//      and promoting design productivity in Xilinx products.
//
//      Therefore use, duplication or disclosure, now and in the 
//      future should give consideration to the productivity 
//      enhancements afforded the user of this code by the author's 
//      efforts.  Thank you for using our products !
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//
// 
// Revision:
//          Aug. 6, 2001     Creation
//
//
// Other modules instanced in this design:
//
/*

BRIEF DESCRIPTION

This version replaces all 5 multipliers with approximations built out of
simple shifts and 5 adders. Also notice that the error introduced, about
1 to 8 percent is all to the downside. Therefore a slight increase in
gain of the components (at the display) will make the differences even
less noticeable.

Color space Conversion for consumer equipment is typically performed on
8 bit data. Of the eight bits, 7 bits are needed to represent the
magnitude of Cr and Cb and 8 bits for Y. The equations used in this
module convert gamma corrected Y (scaled 16 to 235) and CrCb (scaled 16
to 240, with 128 being zero) to gamma corrected RGB (scaled from 0 to
255).

The Virtex II Video Demo Board supports broadcast quality with 10 bit
data.


DETAILED DESCRIPTION:

YCbCr Color Space - YCbCr Color Space was developed as part of the
Recommendation ITU-R BT.601 for worldwide digital component video
standard and is used in television transmissions. Here the color space
is separated into a Luma part (Y) and two Chroma parts (Cb and Cr).

Historically engineers found they could trasmit 1/2 the Chroma values
without extreme picture degradation. Color Space Definition - The human
eye has three types of photoreceptor cells called cones. Stimulating the
cells causes the human brain to "perceive" color. Colors can be
specified, created, and visualized using different color formats or
"color spaces". 

Whatever historical reasons caused color space choices in the past, the
convergence of computers, the Internet, and a wide variety of video
devices, all using different color representations, is forcing the
digital designer today to convert between them. The objective is to have
a common color space that all inputs are converted to before algorithms
and processes are executed.

The converters are useful for a number of markets, such as Multi-media
and image processing. Their basic function is to convert from one color
space to another.

RGB Color Space - RGB color space is a simple definition used in
computer systems. RGB corresponds most closely to the behavior of the
human eye.

RGB is an additive color system. The three primary colors red, green,
and blue are added to form the desired color. Each component has a range
of 0 to 255, with all three 0s producing black and all three 255s
producing 100% saturated, 100% amplitude white.


For 10 bit video
R' = 1.164(Y-64) + 1.596(Cr-512)
G' = 1.164(Y-64) -  .813(Cr-512) - .392(Cb-512)
B' = 1.164(Y-64) +  2.017(Cb-512)

For eight bit video
R' = 1.164(Y-16) + 1.596(Cr-128)
G' = 1.164(Y-16) -  .813(Cr-128) - .392(Cb-128)
B' = 1.164(Y-16) +  2.017(Cb-128)

approximations
--------------

1.164 ~ 1 + .125        -> 1.125 (.039/1.164 = 3% error)
1.596 ~ 1 + .125 + .5   -> 1.625 (.032/1.596 = 2% error)
2.017 ~ 2               -> 2.000 (.017/2.017 = 1% error)
 .813 ~.5 + .25 + .0625 -> .8125 (.0005/.813 = 1% error)
 .382 ~.25 + .125       -> .375  (.007/.382  = 2% error)

It should be noted that this module will produce large excursions beyond
legal values of RGB. These excursions are coherced to the maximum and
minimum RGB values by a follow on module.  The decision to do this was
based on the fact that the follow on format module is used in a number
of places in the pipeline.


Design Information
------------------
xc2v1000-ff896-6

Slices      130
FFs          62
LUTs        183
IO           64
gates     2,455

Minimum period:  16.647ns (Maximum frequency:  60.071MHz)
Maximum net delay:   3.593ns

*/


`timescale 1ns / 100ps

module ycrcb2rgb_v2mult (
rst,
clk,

Fi,           // Low to High signals start of Field One
Vi,           // High signals Vertical Blanking
Hi,           // High signals Horizontal Blanking

Fo,           // Field signal delayed by pipe length
Vo,           // Vertical signal delayed by pipe length
Ho,           // Horizontal signal delayed by pipe length

cei,          // component rate is 1/2 the clock rate
ceo,          // component rate is 1/2 the clock rate

Y_in,
Cr_in,
Cb_in,

R_out,
G_out,
B_out
);

// PIPE_LENGTH must be an even number thereby
// making the length of the pipe an even 
// number of FFs.
parameter PIPE_LENGTH = 2;

input rst, clk, Fi, Vi, Hi, cei;
input [9:0] Y_in, Cr_in, Cb_in;

output [9:0]  R_out, G_out, B_out;
output Fo, Vo, Ho, ceo;

reg [PIPE_LENGTH-1:0] F_rg, V_rg, H_rg, ce_rg;
wire Fo, Vo, Ho, ceo;

reg [9:0] Y_rg, Cr_rg, Cb_rg;

wire [12:0] Y_sub, Cr_sub, Cb_sub;
wire [35:0] P0, P1, P2, P3, P4;
reg [12:0]  Y_1d1640, Cr_0d813, Cr_1d596, Cb_2d017, Cb_0d392;
wire [12:0] R, G, B;

reg [9:0] R_out, G_out , B_out;

integer i;

//-----------------------------------------------------------------------
//
// Shift register delays Fi, Vi, and Hi by the length of the pipe line
//
always @ (posedge clk) begin
  if (rst) begin F_rg <= 0; V_rg <= 0; H_rg <= 0; ce_rg <= 0; end
  else begin
    F_rg[PIPE_LENGTH-1:0] <= {F_rg[PIPE_LENGTH-2:0], Fi};
    V_rg[PIPE_LENGTH-1:0] <= {V_rg[PIPE_LENGTH-2:0], Vi};
    H_rg[PIPE_LENGTH-1:0] <= {H_rg[PIPE_LENGTH-2:0], Hi};
    ce_rg[PIPE_LENGTH-1:0] <= {ce_rg[PIPE_LENGTH-2:0], cei};
  end
end

assign Fo = F_rg[PIPE_LENGTH-1];
assign Vo = V_rg[PIPE_LENGTH-1];
assign Ho = H_rg[PIPE_LENGTH-1];
assign ceo = ce_rg[PIPE_LENGTH-1];



//-----------------------------------------------------------------------
//
// Register Y, Cr, and Cb inputs
//
always @ (posedge clk) begin
  if (rst) begin Y_rg <= 0; Cr_rg <= 0; Cb_rg <= 0; end
  else if (cei) begin Y_rg <= Y_in; Cr_rg <= Cr_in; Cb_rg <= Cb_in; end
  else begin Y_rg <= Y_rg; Cr_rg <= Cr_rg; Cb_rg <= Cb_rg; end
end



//-----------------------------------------------------------------------
//
// Offset Y, Cr, and Cb.
// Note: Internal wires are all 13 bits from here out, to allow for 
// increasing bit extent due to additions, subtractions, and multiplies
// Signs are extended when appropriate.
//
assign Y_sub  = ({3'b000, Y_rg}  - 'd64);  // result always positive
assign Cr_sub = ({3'b000, Cr_rg} - 'd512); // result is positive or negative
assign Cb_sub = ({3'b000, Cb_rg} - 'd512); // result is positive or negative



//-----------------------------------------------------------------------
//
// These equations are v2 multiplier versions of the color space 
// conversion multiplications.
//
/*

Full accuracy equations for 10 bit component video
--------------------------------------------------
R' = 1.164(Y-64) + 1.596(Cr-512)
G' = 1.164(Y-64) -  .813(Cr-512) - .392(Cb-512)
B' = 1.164(Y-64) + 2.017(Cb-512)

use full precision of multiply to experiment with coefficients
1.164 -> I[1:0].F[15:0]  .164 X 2^16 = 094FD or 00 1.001 0100 1111 1101 
0.813 -> I[1:0].F[15:0]  .813 X 2^16 = 06810 or 00 0.110 1000 0001 0000
1.596 -> I[1:0].F[15:0]  .596 X 2^16 = 0CC49 or 00 1.100 1100 0100 1001
2.017 -> I[1:0].F[15:0]  .017 X 2^16 = 1022D or 01 0.000 0010 0010 1101
0.392 -> I[1:0].F[15:0]  .392 X 2^16 = 0322D or 00 0.011 0010 0010 1101

*/

MULT18X18 U1  (.P(P0),  .A(18'h094FD), .B({ Y_sub[12],  Y_sub[12],  Y_sub[12],  Y_sub[12],  Y_sub[12],  Y_sub}));
MULT18X18 U2  (.P(P1),  .A(18'h06810), .B({Cr_sub[12], Cr_sub[12], Cr_sub[12], Cr_sub[12], Cr_sub[12], Cr_sub}));
MULT18X18 U3  (.P(P2),  .A(18'h0CC49), .B({Cr_sub[12], Cr_sub[12], Cr_sub[12], Cr_sub[12], Cr_sub[12], Cr_sub}));
MULT18X18 U4  (.P(P3),  .A(18'h1022D), .B({Cb_sub[12], Cb_sub[12], Cb_sub[12], Cb_sub[12], Cb_sub[12], Cb_sub}));
MULT18X18 U5  (.P(P4),  .A(18'h0322D), .B({Cb_sub[12], Cb_sub[12], Cb_sub[12], Cb_sub[12], Cb_sub[12], Cb_sub}));

// S[1]I[17].F[0] * S[1]I[2].F[15] = S[1]I[20].F[15]

//-----------------------------------------------------------------------
//
// Register outputs of multiply
// Note: P is 24 bits so make P_rg 26 bits and sign smear [25:0]
//
always @ (posedge clk) begin
  if (rst) begin
    Y_1d1640 <= 0;
    Cr_0d813 <= 0;
    Cr_1d596 <= 0;
    Cb_2d017 <= 0;
    Cb_0d392 <= 0;
  end
  else if (ce_rg[1])begin
    Y_1d1640 <= P0[27:15];
    Cr_0d813 <= P1[27:15];
    Cr_1d596 <= P2[27:15];
    Cb_2d017 <= P3[27:15];
    Cb_0d392 <= P4[27:15];
  end
  else begin
    Y_1d1640 <= Y_1d1640;
    Cr_0d813 <= Cr_0d813;
    Cr_1d596 <= Cr_1d596;
    Cb_2d017 <= Cb_2d017;
    Cb_0d392 <= Cb_0d392;
  end
end



//-----------------------------------------------------------------------
//
// Sum the proper outputs from the multiply to form R'G'B'
//
assign R = Y_1d1640 + Cr_1d596;
assign G = Y_1d1640 - Cr_0d813 - Cb_0d392;
assign B = Y_1d1640 + Cb_2d017;




//-----------------------------------------------------------------------
//
// Correct overflows and underflows
//
always @ (posedge clk) begin
  if (rst) R_out <= 0;
  else if (ce_rg[1] & (R[12])) R_out <= 0;              // min value = 0
  else if (ce_rg[1] & (R > 13'h3FC)) R_out <= 13'h3FC;  // max value = 255
  else if (ce_rg[1]) R_out <= R[9:0];                   // otherwise pass
  else R_out <= R_out;                                  // hold
end

always @ (posedge clk) begin
  if (rst) G_out <= 0;
  else if (ce_rg[1] & (G[12])) G_out <= 0;              // min value = 0
  else if (ce_rg[1] & (G > 13'h3FC)) G_out <= 13'h3FC;  // max value = 255
  else if (ce_rg[1]) G_out <= G[9:0];                   // otherwise pass
  else G_out <= G_out;                                  // hold
end

always @ (posedge clk) begin
  if (rst) B_out <= 0;
  else if (ce_rg[1] & (B[12])) B_out <= 0;              // min value = 0
  else if (ce_rg[1] & (B > 13'h3FC)) B_out <= 13'h3FC;  // max value = 255
  else if (ce_rg[1]) B_out <= B[9:0];                   // otherwise pass
  else B_out <= B_out;                                  // hold
end


endmodule