-- VHDL Test Bench Created from source file fifo_new.vhd -- 10:13:22 04/05/2005
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

    COMPONENT fifo_new
    PORT(
       rstn : IN std_logic;
       clk16x : IN std_logic;
       datain : IN std_logic_vector(7 downto 0);
       rdpulse : IN std_logic;
       wrpulse : IN std_logic;          
       sout : OUT std_logic;
       clrrxrdy : OUT std_logic;
       full : buffer std_logic;
       empty : buffer std_logic;
       Wraddr_watch: out std_logic_vector(4 downto 0);
       Rdaddr_watch: out std_logic_vector(4 downto 0);
       Intsignal:  out std_logic
       );
    END COMPONENT;

    SIGNAL rstn :  std_logic  := '0';
    SIGNAL clk16x :  std_logic  :='1';
    SIGNAL datain :  std_logic_vector(7 downto 0) :="00000000";
    SIGNAL rdpulse :  std_logic :='0';
    SIGNAL wrpulse :  std_logic;
    SIGNAL sout :  std_logic;
    SIGNAL clrrxrdy :  std_logic;
    SIGNAL full :  std_logic;
    SIGNAL empty :  std_logic;
    SIGNAL wraddr_watch : std_logic_vector(4 downto 0);
    SIGNAL rdaddr_watch : std_logic_vector(4 downto 0);

    SIGNAL Intsignal  : std_logic;
       
BEGIN

    uut: fifo_new PORT MAP(
       rstn => rstn,
       clk16x => clk16x,
       datain => datain,
       rdpulse => rdpulse,
       wrpulse => wrpulse,
       sout => sout,
       clrrxrdy => clrrxrdy,
       full => full,
       empty => empty,
       wraddr_watch => wraddr_watch,
       rdaddr_watch => rdaddr_watch,
       Intsignal => Intsignal
    );          


-- *** Test Bench - User Defined Section ***
    rstn <=  '1'  after  5 us;
    clk16x<= not clk16x after 0.5us;

    wrpulse <= '0' after 10us,
               '1' after 12us,
               '0' after 25us,
               '1' after 228us,
               '0' after 246us;

    datain  <=  "00000001" after 12 us,
                "00000010" after 13 us,
                "00000011" after 14 us,
                "00000010" after 15 us,
                "00000010" after 16 us,
                "00110010" after 17 us,
                "00000010" after 18 us,
                "00000010" after 19 us,
                "00000000" after 20 us,
                "00000010" after 21 us,
                "00110010" after 22 us,
                "00000000" after 23 us,
                "01000010" after 24 us,
                "00000000" after 25 us,
                "10000010" after 26 us,
                "00010010" after 27 us,
                "00000010" after 228 us,
                "00100011" after 229 us,
                "01100010" after 230 us,
                "00000001" after 231 us,
                "00000010" after 232 us,
                "00000011" after 233 us,
                "00000010" after 234 us,
                "00000010" after 235 us,
                "00110010" after 236 us,
                "00000010" after 237 us,
                "00000010" after 238 us,
                "00000000" after 239 us,
                "00000010" after 240 us,
                "00110010" after 241 us,
                "00000000" after 242 us,
                "01000010" after 243 us,
                "00000000" after 244 us,
                "10000010" after 245 us,
                "00010010" after 246 us,
                "00000010" after 247 us,
                "00100011" after 248 us,
                "01100010" after 249 us;


   tb : PROCESS
   BEGIN
      wait; -- will wait forever,to end the process
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;