`timescale 1us / 1us
						
module PULSE_WIDTH_TEST;		
    reg    CLK, CLKX, RST;               
    wire   [16:0] WIDTH;     
          
						
    PULSE_WIDTH PULSE_WIDTH  (CLK, CLKX, RST, WIDTH);

    always  #500   CLK=~CLK;

   initial
      begin:CLOCK
        CLKX=0; 
        forever  
          begin  
           #6000 CLKX=~CLKX;
          end
      end

    initial
      begin:SIMULATION
        CLK=0; RST=1; 
        #10  RST=0;
        #10  RST=1;                     
        #50000  $finish;
        disable CLOCK;
      end

endmodule