?? pulse_level_test.v
字號:
`timescale 1us / 1us
module PULSE_LEVEL_TEST;
reg CLK, CLKX, RST;
wire [16:0] H_LEVEL;
wire [7:0] L_LEVEL;
PULSE_LEVEL PULSE_LEVEL (CLK, CLKX, RST, H_LEVEL, L_LEVEL);
always #500 CLK=~CLK;
initial
begin:CLOCK
parameter ON=6000, OFF=2000;
CLKX=0;
forever
begin
#OFF CLKX=1'b1;
#ON CLKX=1'b0;
end
end
initial
begin
CLK=0; RST=1;
#100 RST=0;
#100 RST=1;
#50000 $finish;
disable CLOCK;
end
endmodule
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -