?? 條件賦值:使用列舉類型.vhd
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-- Selected Signal Assignment with Enumeration Type
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LUNCH, DINNER, MIDNIGHT_SNACK);
END meals_pkg;
USE work.meals_pkg.all;
ENTITY selsigen IS
PORT
(
previous_meal : IN MEAL;
next_meal : OUT MEAL
);
END selsigen;
ARCHITECTURE maxpld OF selsigen IS
BEGIN
WITH previous_meal SELECT
next_meal <= BREAKFAST WHEN DINNER | MIDNIGHT_SNACK,
LUNCH WHEN BREAKFAST,
DINNER WHEN LUNCH;
END maxpld;
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