-------------------------------------------------------------------- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.-- -------------------------------------------------------------------- State machine description using enumerated types---- This is a typical example of a state machine description.--   Two processes, one to update the state on a clock plus--   handles reset, and one to calculate the next state and--   the outputs in a case statement---- State encoding on state_t will be done by CORE. Binary encoding is the-- default, option -encoding provides alternatives (onehot, gray, random)-- -- This description implements a traffic light controller----     Version 1.1 : Original Creation --     Version 1.2 : Modified to std_logic types--     Version 2.1 : Improved design with CASE instead of if-then-else--		--	download from: www.pld.com.cn & www.fpga.com.cn ----------------------------------------------------------------LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY traffic IS    PORT (clock, sensor1, sensor2, reset : IN std_logic;	  red1, yellow1, green1, red2, yellow2, green2 : OUT std_logic);END ;ARCHITECTURE eXemplar OF traffic IS    TYPE state_t IS ( ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7 );    SIGNAL state, nxstate : state_t;BEGINupdate_state :	-- Update the state on the clock edge    PROCESS (reset, clock)    BEGIN        IF (reset='1') THEN	    state <= ST0 ;        ELSIF clock'event and clock='1' THEN	    state <= nxstate ;	END IF ;    END PROCESS;transitions :	-- set the outputs and next state    PROCESS (state, sensor1, sensor2)    BEGIN        -- Default values for the outputs        red1 <= '0'; yellow1 <= '0'; green1 <= '0';        red2 <= '0'; yellow2 <= '0'; green2 <= '0';        -- Make sure to always set a value for nxstate,         -- or unwanted latches will occur.	CASE state IS	    WHEN ST0 =>	        green1 <= '1';	        red2 <= '1';	        IF sensor2 = sensor1 THEN		    nxstate <= ST1;	        ELSIF (sensor1 = '0' AND sensor2 = '1') THEN		    nxstate <= ST2;	        ELSE		    nxstate <= ST0;	        END IF;	    WHEN ST1 =>       	        green1 <= '1';	        red2 <= '1';	        nxstate <= ST2;	    WHEN ST2 =>       	        green1 <= '1';	        red2 <= '1';	        nxstate <= ST3;	    WHEN ST3 =>       	        yellow1 <= '1';	        red2 <= '1';	        nxstate <= ST4;	    WHEN ST4 =>       	        red1 <= '1';	        green2 <= '1';	        IF (sensor1 = '0' AND sensor2 = '0') THEN		    nxstate <= ST5;	        ELSIF (sensor1 = '1' AND sensor2 = '0') THEN		    nxstate <= ST6;	        ELSE		    nxstate <= ST4;	        END IF;	    WHEN ST5 =>       	        red1 <= '1';	        green2 <= '1';	        nxstate <= ST6;	    WHEN ST6 =>       	        red1 <= '1';	        green2 <= '1';	        nxstate <= ST7;	    WHEN ST7 =>       	        red1 <= '1';	        yellow2 <= '1';	        nxstate <= ST0;	END CASE;    END PROCESS;END eXemplar;