// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
//                     5555 NE Moore Court
//                     Hillsboro, OR 97214
//                     U.S.A
//
//                     TEL: 1-800-Lattice (USA and Canada)
//                          408-826-6000 (other locations)
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//                     web: http://www.latticesemi.com/
//                     email: techsupport@latticesemi.com
//
// --------------------------------------------------------------------
//
// This is the test bench module of the SDR SDRAM controller reference
// design.  It is highly recommanded to download simulation modules
// from the SDRAM venders when you are working on the modification of
// the SDR SDRAM controller reference design.
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V0.1 :| Nagaraj Chekka    :| 07/29/03  :| Pre-Release
// --------------------------------------------------------------------

`timescale 1ns / 1ps

module ddr_tb;

`include "ddr_par.v"

wire              sys_r_wn;         // read/write#
wire              sys_adsn;         // address strobe
wire              sys_dly_200us;    // ddr power and clock stable for 100 us
wire              clk;              // ddr clock
wire              sys_reset;        // reset signal
wire [23:0]       sys_add;          // address bus
wire [15:0]       sysd;             // data bus
wire [1:0]        sys_dmsel;        // Data mask enables
wire              sys_init_done;    // initialization completed, ready for normal operation

wire [7:0]        ddr_dq;           // ddr data
wire [11:0]       ddr_add;          // ddr address
wire [1:0]        ddr_ba;           // ddr bank address
wire              ddr_cke;          // ddr clock enable
wire              ddr_csn;          // ddr chip select
wire              ddr_rasn;         // ddr row address
wire              ddr_casn;         // ddr column select
wire              ddr_wen;          // ddr write enable
wire              ddr_dqm;          // ddr write data mask

//=============================================================================
// DDR TOP 
//=============================================================================
ddr_top UUT
  (
   // Clock and reset signals
   .clk             (clk),              // ddr clock
   .reset_n         (reset_n),          // reset signal
   // Systen interface signals
   .sys_r_wn        (sys_r_wn),         // read/write#
   .sys_adsn        (sys_adsn),         // address strobe
   .sys_dly_200us   (sys_dly_200us),    // ddr power and clock stable for 200 us
   .sys_add         (sys_add),          // address bus
   .sysd            (sysd),             // data bus
   .sys_init_done   (sys_init_done),    // initialization completed, ready for normal operation
   .sys_rdyn        (sys_rdyn),         // Ready signal
   .sys_dmsel       (sys_dmsel),        // Ready signal
   //DDR interface signals
   .ddr_clk         (ddr_clk),          // DDR clock
   .ddr_clkn        (ddr_clkn),         // DDR -ve clock 
   .ddr_dq          (ddr_dq),           // ddr data
   `ifdef SDF_SIM
   .ddr_dqm_0       (ddr_dqm),          // ddr write data mask
   .ddr_dqs_0       (ddr_dqs),          // ddr data strobe
   `else
   .ddr_dqm         (ddr_dqm),          // ddr write data mask
   .ddr_dqs         (ddr_dqs),          // ddr data strobe
   `endif
   .ddr_add         (ddr_add),          // ddr address
   .ddr_ba          (ddr_ba),           // ddr bank address
   .ddr_cke         (ddr_cke),          // ddr clock enable
   .ddr_csn         (ddr_csn),          // ddr chip select
   .ddr_rasn        (ddr_rasn),         // ddr row address
   .ddr_casn        (ddr_casn),         // ddr column select
   .ddr_wen         (ddr_wen)           // ddr write enable
   );

//=============================================================================
// Stimulus 
//=============================================================================

stimulus u1_stimulus
  (
   .clk             (clk),
   .reset_n         (reset_n),
   .sys_add         (sys_add),
   .sys_adsn        (sys_adsn),
   .sys_r_wn        (sys_r_wn),
   .sysd            (sysd),
   .sys_dly_200us   (sys_dly_200us),
   .sys_rdyn        (sys_rdyn),
   .sys_dmsel       (sys_dmsel),
   .sys_init_done   (sys_init_done)
   );


//=============================================================================
// DDR Model
//=============================================================================

// Module "mt46v16m8" can be downloaded from Micro's web site.
// 16Meg x 8  (Has 4k rows, 1k col, 4banks)
mt46v16m8 U1_DDR
  (
   .Dq     (ddr_dq), 
   .Dqs    (ddr_dqs), 
   .Addr   (ddr_add), 
   .Ba     (ddr_ba), 
   .Clk    (ddr_clk), 
   .Clk_n  (ddr_clkn), 
   .Cke    (ddr_cke), 
   .Cs_n   (ddr_csn), 
   .Ras_n  (ddr_rasn), 
   .Cas_n  (ddr_casn), 
   .We_n   (ddr_wen), 
   .Dm     (ddr_dqm)
   );



initial begin
   $recordfile ("ddrref.trn");
   $recordvars;
end


initial begin
     
`ifdef SDF_SIM
   $sdf_annotate("../par/run/Map_Rev_1/Par_Rev_1/ddr_top.sdf",UUT,, "ddr_top_sdf.log");
`endif
     
end

endmodule