?? div20pll.sim.rpt
字號:
Simulator report for Div20PLL
Thu Mar 01 10:44:08 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Simulator Summary
3. Simulator Settings
4. Simulation Waveforms
5. Coverage Summary
6. Complete 1/0-Value Coverage
7. Missing 1-Value Coverage
8. Missing 0-Value Coverage
9. Simulator INI Usage
10. Simulator Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------+
; Simulator Summary ;
+-----------------------------+--------------+
; Type ; Value ;
+-----------------------------+--------------+
; Simulation Start Time ; 0 ps ;
; Simulation End Time ; 30.0 us ;
; Simulation Netlist Size ; 10 nodes ;
; Simulation Coverage ; 87.50 % ;
; Total Number of Transitions ; 10199 ;
; Simulation Breakpoints ; 0 ;
; Family ; Stratix ;
; Device ; EP1S10F484C5 ;
+-----------------------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------+---------------+
; Simulation mode ; Timing ; Timing ;
; Start time ; 0 ns ; 0 ns ;
; Vector input source ; D:\so2006\cpld-pro\數字環\DPLL0226\Div20PLL.vwf ; ;
; Add pins automatically to simulation output waveforms ; On ; On ;
; Check outputs ; Off ; Off ;
; Report simulation coverage ; On ; On ;
; Display complete 1/0 value coverage report ; On ; On ;
; Display missing 1-value coverage report ; On ; On ;
; Display missing 0-value coverage report ; On ; On ;
; Detect setup and hold time violations ; Off ; Off ;
; Detect glitches ; Off ; Off ;
; Disable timing delays in Timing Simulation ; Off ; Off ;
; Generate Signal Activity File ; Off ; Off ;
; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Glitch Filtering ; Off ; Off ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 87.50 % ;
; Total nodes checked ; 10 ;
; Total output ports checked ; 8 ;
; Total output ports with complete 1/0-value coverage ; 7 ;
; Total output ports with no 1/0-value coverage ; 1 ;
; Total output ports with no 1-value coverage ; 1 ;
; Total output ports with no 0-value coverage ; 1 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-------------------+-------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------+-------------------+------------------+
; |Div20PLL|reg[1] ; |Div20PLL|reg[1] ; regout ;
; |Div20PLL|rst~29 ; |Div20PLL|reg[0] ; regout ;
; |Div20PLL|dly3reg ; |Div20PLL|dly3reg ; regout ;
; |Div20PLL|reg[3] ; |Div20PLL|reg[3] ; regout ;
; |Div20PLL|reg[4] ; |Div20PLL|reg[4] ; regout ;
; |Div20PLL|clock ; |Div20PLL|clock ; combout ;
; |Div20PLL|clkout ; |Div20PLL|clkout ; padio ;
+-------------------+-------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------+
; Missing 1-Value Coverage ;
+------------------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------+------------------+------------------+
; |Div20PLL|rst~29 ; |Div20PLL|rst~29 ; combout ;
+------------------+------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------+
; Missing 0-Value Coverage ;
+------------------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------+------------------+------------------+
; |Div20PLL|rst~29 ; |Div20PLL|rst~29 ; combout ;
+------------------+------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Mar 01 10:44:06 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Div20PLL -c Div20PLL
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 87.50 %
Info: Number of transitions in simulation is 10199
Info: Vector file Div20PLL.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Mar 01 10:44:07 2007
Info: Elapsed time: 00:00:02
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