--*********************************************--
--
--*******		Div20PLL.vhd		***********--
--
--*********************************************--
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;

Entity Div20PLL is Port(
	clock						:in std_logic;	--80M local clk
	flow						:in std_logic;	--4M data flow
	clkout						:out std_logic	--4M CLK
	);
End Div20PLL;

Architecture myFavor of Div20PLL is

Function filter(reg : std_logic_vector; clr,d : std_logic)
		return std_logic_vector is
variable rg 			: std_logic_vector(1 downto 0);
Begin
	if clr = '1' then
		return "00";
	end if;	
	rg := reg;
	if d = '1' then
	   rg := not rg(0) & rg(1);
	end if;
	return rg;
End filter;
	
signal fa,fb,saltus,cmp				:std_logic;
signal pulcnt,reg					:std_logic_vector(4 downto 0);
signal phase						:std_logic_vector(1 downto 0);
signal miss,dly3reg,enclk			:std_logic;
signal clk4M,dly4M,posEdge			:std_logic;
signal los,lead,lag,syn				:std_logic;
signal dec,inc						:std_logic;
signal pulse,rst					:std_logic;
signal losreg,leadreg,lagreg		:std_logic_vector(1 downto 0);

Begin
Process(clock) begin
 if rising_edge(clock) then
	fa <= flow;
	fb <= fa;
	dly3reg <= reg(3);
	dly4M <= not clk4M;
	cmp <= pulcnt(3) and pulcnt(2) and pulcnt(1) and pulcnt(0);
 end if;
End process;
saltus <= fa xor fb;
posEdge <= dly4M and clk4M and pulse;
--expect posEdge locate pulcnt(10)
pulse <= not pulcnt(4);

Process(clock) begin
 if rising_edge(clock) then
	if saltus = '1' then
		pulcnt <= "00000";
	elsif pulcnt(4) = '0' then
		pulcnt <= pulcnt + 1;
	else null;
	end if;
 end if;
End process;

Process(clock) begin
 if rising_edge(clock) then
	if pulse = '0' then
		phase <= "00";
	elsif posEdge = '1' then
		phase <= pulcnt(3 downto 2);
	else null;
	end if;
 end if;
End process;

rst <= (reg(2) and not reg(1) and reg(0)) or miss;
Process(clock) begin
 if rising_edge(clock) then
	if rst = '1' then
		reg <= "00000";
	elsif inc = '1' then
		reg <= not reg(1 downto 0) & reg(4 downto 2);
	elsif dec = '1' then
		reg <= reg;
	else
		reg <= not reg(0) & reg(4 downto 1);
	end if;
 end if;
End process;
enclk <= reg(3) and not dly3reg;
--expect reverse clk4M when reg = "11000" 
Process(clock) begin
 if rising_edge(clock) then
	if rst = '1' then
		clk4M <= '1';
	elsif enclk = '1' then
		clk4M <= not clk4M;
	else null;
	end if;
 end if;
End process;

los <= (phase(1) nor phase(0)) and cmp;
lag <= phase(1) and phase(0) and cmp;
lead <= not phase(1) and phase(0) and cmp;
syn <= phase(1) and not phase(0) and cmp;

Process(clock) begin
 if rising_edge(clock) then
	losreg <= filter(losreg,syn,los);
	leadreg <= filter(leadreg,syn,lead);
	lagreg <= filter(lagreg,syn,lag);
 end if;
End process;
miss <= losreg(1) and losreg(0) and los;
dec <= leadreg(1) and leadreg(0) and lead;
inc <= lagreg(1) and lagreg(0) and lag;
clkout <= clk4M;
End myFavor;