?? bit_synchronous.rpt
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Project Information d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 02/15/2007 14:33:14
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
BIT_SYNCHRONOUS
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
bit_synchronous
EPM3064ALC44-4 5 2 0 44 4 68 %
User Pins: 5 2 0
Project Information d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':40' stuck at GND
Warning: Flipflop ':42' stuck at GND
Warning: Flipflop ':45' stuck at GND
Project Information d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
** FILE HIERARCHY **
|lpm_add_sub:315|
|lpm_add_sub:315|addcore:adder|
|lpm_add_sub:315|addcore:adder|addcore:adder0|
|lpm_add_sub:315|altshift:result_ext_latency_ffs|
|lpm_add_sub:315|altshift:carry_ext_latency_ffs|
|lpm_add_sub:315|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:636|
|lpm_add_sub:636|addcore:adder|
|lpm_add_sub:636|addcore:adder|addcore:adder1|
|lpm_add_sub:636|addcore:adder|addcore:adder0|
|lpm_add_sub:636|altshift:result_ext_latency_ffs|
|lpm_add_sub:636|altshift:carry_ext_latency_ffs|
|lpm_add_sub:636|altshift:oflow_ext_latency_ffs|
Device-Specific Information:d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
bit_synchronous
***** Logic for device 'bit_synchronous' compiled without errors.
Device: EPM3064ALC44-4
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
R R R R
E E E E
S S V S S
c E E C E E
l R R C R R
o V V I G G G G G V V
c E E N N N N N N E E
k D D T D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
code_sel | 8 38 | #TDO
en_clock | 9 37 | RESERVED
GND | 10 36 | GND
fast | 11 35 | VCCIO
fb | 12 EPM3064ALC44-4 34 | code256
#TMS | 13 33 | RESERVED
RESERVED | 14 32 | #TCK
VCCIO | 15 31 | RESERVED
RESERVED | 16 30 | GND
GND | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V b R R R R
E E E E N C i E E E E
S S S S D C t S S S S
E E E E I _ E E E E
R R R R N s R R R R
V V V V T y V V V V
E E E E n E E E E
D D D D c D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
bit_synchronous
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 6/ 8( 75%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 13/16( 81%) 1/ 7( 14%) 0/16( 0%) 21/36( 58%)
C: LC33 - LC48 16/16(100%) 2/ 8( 25%) 6/16( 37%) 23/36( 63%)
D: LC49 - LC64 15/16( 93%) 2/ 7( 28%) 1/16( 6%) 16/36( 44%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 11/30 ( 36%)
Total logic cells used: 44/64 ( 68%)
Total shareable expanders used: 4/64 ( 6%)
Total Turbo logic cells used: 44/64 ( 68%)
Total shareable expanders not available (n/a): 3/64 ( 4%)
Average fan-in: 8.04
Total fan-in: 354
Total input pins required: 5
Total output pins required: 2
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 44
Total flipflops required: 32
Total product terms required: 126
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information:d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
bit_synchronous
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
6 (11) (A) INPUT 0 0 0 0 0 0 8 clock
8 (5) (A) INPUT 0 0 0 0 0 1 2 code_sel
9 (4) (A) INPUT 0 0 0 0 0 0 12 en_clock
11 (3) (A) INPUT 0 0 0 0 0 0 2 fast
12 (1) (A) INPUT 0 0 0 0 0 0 4 fb
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
bit_synchronous
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
24 33 C FF t 0 0 0 0 12 0 0 bit_sync
34 51 D OUTPUT t 0 0 0 1 2 0 0 code256
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
bit_synchronous
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 54 D SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:315|addcore:adder|addcore:adder0|result_node3
(37) 53 D SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:315|addcore:adder|addcore:adder0|result_node4
- 29 B SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node2
- 28 B SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node3
- 24 B SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node4
- 23 B SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node5
- 22 B SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node6
- 39 C SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node7
- 43 C SOFT t 1 0 0 0 9 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder1|result_node0
- 45 C SOFT t 0 0 0 0 10 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder1|result_node1
(31) 46 C SOFT t 0 0 0 0 11 0 1 |LPM_ADD_SUB:636|addcore:adder|addcore:adder1|result_node2
- 63 D DFFE t 0 0 0 2 3 0 2 m2 (:10)
- 60 D DFFE t 0 0 0 2 1 0 2 m1 (:11)
(38) 56 D DFFE t 0 0 0 2 1 1 3 m0 (:12)
- 55 D TFFE t 0 0 0 2 0 1 2 fangbo (:13)
- 52 D DFFE t 0 0 0 2 6 0 5 count254 (:18)
(40) 62 D DFFE t 0 0 0 2 6 0 6 count253 (:19)
- 61 D TFFE t 0 0 0 2 2 0 6 count252 (:20)
- 59 D TFFE t 0 0 0 2 1 0 7 count251 (:21)
- 58 D TFFE t 0 0 0 2 5 0 8 count250 (:22)
(39) 57 D DFFE t 0 0 0 2 5 1 11 clk_480KHz (:23)
- 50 D DFFE t 0 0 0 3 2 0 1 q (:24)
(33) 49 D DFFE t 1 0 1 3 3 0 8 bit_pulse (:25)
(27) 37 C DFFE t 0 0 0 0 14 1 16 count187510 (:26)
(18) 21 B DFFE t 0 0 0 0 14 1 17 count18759 (:27)
(19) 20 B DFFE t 0 0 0 0 14 1 18 count18758 (:28)
(26) 36 C DFFE t 0 0 0 0 13 1 19 count18757 (:29)
- 34 C DFFE t 0 0 0 0 14 1 20 count18756 (:30)
- 47 C DFFE t 0 0 0 0 13 1 21 count18755 (:31)
- 18 B DFFE t 0 0 0 0 14 1 22 count18754 (:32)
(21) 17 B DFFE t 0 0 0 0 14 1 23 count18753 (:33)
- 38 C DFFE t 0 0 0 0 13 1 24 count18752 (:34)
(28) 40 C TFFE t 0 0 0 0 13 1 24 count18751 (:35)
(29) 41 C TFFE t 0 0 0 0 13 1 24 count18750 (:36)
(16) 25 B DFFE t 0 0 0 0 1 0 1 preset187510 (:37)
- 26 B DFFE t 0 0 0 0 1 0 1 preset18759 (:38)
(20) 19 B DFFE t 0 0 0 0 1 0 1 preset18758 (:39)
- 27 B DFFE t 0 0 0 0 1 0 1 preset18756 (:41)
- 42 C DFFE t 3 0 1 1 12 0 1 preset18754 (:43)
- 44 C DFFE t 0 0 0 1 12 0 1 preset18753 (:44)
(32) 48 C DFFE t 2 0 1 0 12 0 1 preset18751 (:46)
(25) 35 C DFFE t 0 0 0 0 12 0 1 preset18750 (:47)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:d:\so2006\cpld-pro\quartus6\pll1218\bit_synchronous.rpt
bit_synchronous
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC29 |LPM_ADD_SUB:636|addcore:adder|addcore:adder0|result_node2
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