?? uart_int_tb.vhd

?? 利用VHDL語言開發(fā)一個UART的源代碼
?? VHD
?? 第 1 頁 / 共 3 頁
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  end process SIN_proc;

-----------------------------------------------------------------------
-- Test UART Transmitter/Receiver Functions
-----------------------------------------------------------------------
  UART_Stim_Proc : process
    variable i : integer;
  begin

    -- Reset and Intialization
    MR <= '1';

    CS <= '0';
    ADSn <= '1';
    A <= "111";
    DIN <= "11111111";

    CTSn <= '1';
    DCDn <= '1';
    DSRn <= '1';
    RIn  <= '1';

    wait for (9.5*CLK_PERIOD + 3 ns);

    MR <= '0';

    wait for (0.5*CLK_PERIOD - 3 ns);


    -- Test 1 ----------------------------------------------------
    --   Receiver Line Status Interrupt test
    if not EOT then
       wait until EOT;
    end if;
    TestID <= 1;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 1, enable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, even parity selected
    --   bit 3 : 0, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00000011",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is pending due to Overrun
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000110"
      report"Invalid IIR"
      severity failure;

    -- Read and check LSR (check if "Overrun Error" flag at bit 1 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100011"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is low
    -- Overrun Error Interrupt should be reset after reading LSR
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Overrun Error" flag at bit 1 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01010110"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01010110"
      report"Invalid RBR"
      severity failure;


    -- Test 2 ----------------------------------------------------
    --   Level 2 interrupt test
    --   Receiver Data Available Interrupt test
    if not EOT then
       wait until EOT;
    end if;
    TestID <= 2;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00011011",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is pending due to Receiver Data Available
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000100"
      report"Invalid IIR"
      severity failure;

    -- Read and Check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack(0) = '1'
      report"Receiver Data Ready bit in LSR is not set"
      severity failure;

    -- Check if IIR is not changed due to LSR read
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000100"
      report"Invalid IIR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is reset due to RBR read
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000001"
      report"Invalid IIR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is pending due to Receiver Data Available
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000100"
      report"Invalid IIR"
      severity failure;

    -- Read and Check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack(0) = '1'
      report"Receiver Data Ready bit in LSR is not set"
      severity failure;

    -- Check if IIR is not changed due to LSR read
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000100"
      report"Invalid IIR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010011"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is reset due to RBR read
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000001"
      report"Invalid IIR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;


    -- Test 3 ----------------------------------------------------
    --   Level 3 interrupt test
    --   Transmitter Holding Register Empty Interrupt test
    if not EOT then
       wait until EOT;
    end if;
    TestID <= 3;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 1, enable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00000010",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00001011",CS,ADSn,WRn,A,DIN);

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is pending due to THR empty
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000010"
      report"Invalid IIR"
      severity failure;

    -- Write data into THR, 1st time
    write_reg (THR,"00010001",CS,ADSn,WRn,A,DIN);
    wait for (8*CLK_PERIOD); -- wait longer for data to transfer from THR to TSR

    -- Write data into THR, 2nd time
    write_reg (THR,"00100010",CS,ADSn,WRn,A,DIN);

    -- Check if INTR is reset due to THR write
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000001"
      report"Invalid IIR"
      severity failure;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if 2nd INTR is pending due to THR empty
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000010"
      report"Invalid IIR"
      severity failure;

    -- Write data into THR, 3nd time
    write_reg (THR,"00110011",CS,ADSn,WRn,A,DIN);
    
    -- Clear IER
    write_reg (IER,"00000000",CS,ADSn,WRn,A,DIN);


    -- Test 4 ----------------------------------------------------
    --   Level 4 interrupt test
    --   MODEM Status Interrupt test
    if not EOT then
       wait until EOT;
    end if;
    TestID <= 4;
    
    -- IER Intialization
    --   bit 3 : 1, enable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00001000",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00001011",CS,ADSn,WRn,A,DIN);

    -- Check if INTR is currently reset to show no interrupt pending
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    intLevel <= conv_integer(regData_readBack(2 downto 1));
    assert regData_readBack = "00000001"
      report"Invalid IIR"
      severity failure;

    -- Read MSR and check
    read_reg (MSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00000000"
      report"Invalid MSR"
      severity failure;

    CTSn <= '0'; -- MODEM signal changed
?? 文件大小 311 K
?? 上傳用戶 bonylee_java
?? 所屬分類 VHDL/FPGA/Verilog
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