?? uart_int_tb.vhd
字號:
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if INTR is pending due to MODEM Status change
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000000"
report"Invalid IIR"
severity failure;
-- Read MSR to reset the MODEM Status Interrupt
read_reg (MSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "00010001"
report"Invalid MSR"
severity failure;
-- Read MSR and check
read_reg (MSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "00010000"
report"Invalid MSR"
severity failure;
-- Check if INTR is reset to no interrupt pending
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000001"
report"Invalid IIR"
severity failure;
CTSn <= '1'; -- MODEM signal changed again
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if INTR is pending due to MODEM Status change
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000000"
report"Invalid IIR"
severity failure;
-- Read MSR to reset the MODEM Status Interrupt
read_reg (MSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "00000001"
report"Invalid MSR"
severity failure;
-- Read MSR and check
read_reg (MSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "00000000"
report"Invalid MSR"
severity failure;
-- Check if INTR is reset to no interrupt pending
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000001"
report"Invalid IIR"
severity failure;
-- Test 5 ----------------------------------------------------
-- Mixed level 1,2 interrupt test
if not EOT then
wait until EOT;
end if;
TestID <= 5;
-- IER Intialization
-- bit 3 : 0, disable modem status interrupt
-- bit 2 : 1, enable receiver line status interrupt
-- bit 1 : 0, disable tranmitter holding register empty interrupt
-- bit 0 : 1, enable received data available interrupt
write_reg (IER,"00000101",CS,ADSn,WRn,A,DIN);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 1, 8 data bit (bit[1-0]="11")
-- bit 0 : 1, 8 data bit (bit[1-0]="11")
write_reg (LCR,"00011011",CS,ADSn,WRn,A,DIN);
-- trigger okToReceiveSIN to get character from SIN
okToReceiveSIN <= '1',
'0' after 1 ns;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if INTR is pending due to Receiver Data Available
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000100"
report"Invalid IIR"
severity failure;
-- Read and Check LSR (check if "Data Ready" flag at bit 0 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack(0) = '1'
report"Receiver Data Ready bit in LSR is not set"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if INTR is pending due to Parity Error
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000110"
report"Invalid IIR"
severity failure;
-- Read and check RBR
-- A RBR read clears this RxRDY flag in LSR bit 1. Because of this, a
-- Receiver Data Available interrupt will not be generated right after
-- the Parity Error interrupt is cleared by LSR read.
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Parity Error" flag at bit 2 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100100"
report"Invalid LSR"
severity failure;
-- Read and check LSR (read again to see if it's changed by LSR read)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
-- Test 6 ----------------------------------------------------
-- Mixed level 1,2,3 interrupt test
if not EOT then
wait until EOT;
end if;
TestID <= 6;
-- IER Intialization
-- bit 3 : 0, disable modem status interrupt
-- bit 2 : 1, enable receiver line status interrupt
-- bit 1 : 1, enable tranmitter holding register empty interrupt
-- bit 0 : 1, enable received data available interrupt
write_reg (IER,"00000111",CS,ADSn,WRn,A,DIN);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 1, 8 data bit (bit[1-0]="11")
-- bit 0 : 1, 8 data bit (bit[1-0]="11")
write_reg (LCR,"00001011",CS,ADSn,WRn,A,DIN);
-- trigger okToReceiveSIN to get character from SIN
okToReceiveSIN <= '1',
'0' after 1 ns;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if INTR is pending due to THR empty
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000010"
report"Invalid IIR"
severity failure;
-- Write data into THR, 1st time
write_reg (THR,"00001011",CS,ADSn,WRn,A,DIN);
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if 2nd INTR is pending due to THR empty
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000010"
report"Invalid IIR"
severity failure;
-- Write data into THR, 2nd time
write_reg (THR,"00011011",CS,ADSn,WRn,A,DIN);
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if 3rd INTR is pending due to Receiver Data Available
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000100"
report"Invalid IIR"
severity failure;
-- Wait until THR empty
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "THRE" flag at bit 5 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(5) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Check if IIR is reset due to THR empty
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000010"
report"Invalid IIR"
severity failure;
-- Write data into THR, 3rd time
write_reg (THR,"00101011",CS,ADSn,WRn,A,DIN);
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Check if 3rd INTR is pending due to Parity Error
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack = "00000110"
report"Invalid IIR"
severity failure;
-- Read and check RBR
-- A RBR read clears this RxRDY flag in LSR bit 1. Because of this, a
-- Receiver Data Available interrupt will not be generated right after
-- the Parity Error interrupt is cleared by LSR read.
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Parity Error" flag at bit 2 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack(2) = '1'
report"Invalid LSR"
severity failure;
-- Check if IIR is reset due to LSR read
read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
intLevel <= conv_integer(regData_readBack(2 downto 1));
assert regData_readBack /= "00000110"
report"Invalid IIR"
severity failure;
-- Read and check LSR (check if "Parity Error" flag is cleared by LSR read)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack(2) = '0'
report"Invalid LSR"
severity failure;
-- Clear IER
write_reg (IER,"00000000",CS,ADSn,WRn,A,DIN);
-- end of tests ----------------------------------------------
assert (false)
report"End of UART Interrupt Tests ....."
severity failure;
end process UART_Stim_Proc;
-- *** end of test bench ***
end;
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