-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
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--                     Lattice Semiconductor Corporation
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--                     web: http://www.latticesemi.com/
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-- --------------------------------------------------------------------
--
--  Project:           Universal Asynchronous Receiver Transmitter
--  File:              rxcver.vhd
--  Title:             rxcver
--  Design Library:    IEEE
--  Dependencies:      IEEE.std_logic_1164.all
--                     IEEE.std_logic_unsigned.all
--  Description:       VHDL file for the UART Receiver Module
--
--    <Global reset and clock>
--      Reset       : Master reset
--      Clk16X      : UART internal clock
--
--    <Register>
--      RBR         : Receiver Buffer Register
--
--    <Rising edge of RBR, LSR read strobes>
--      RbrRDn_re   : one Clk16X width pulse indicating rising edge of RbrRDn_r
--      LsrRDn_re   : one Clk16X width pulse indicating rising edge of LsrRDn_r
--
--    <Receiver input>
--      SIN         : Receiver serial input
--
--    <Receiver control>
--      Databits    : "00"=5-bit, "01"=6-bit, "10"=7-bit, "11"=8-bit
--      ParityEnable: '0'=Parity Bit Enable, '1'=Parity Bit Disable
--      ParityEven  : '0'=Even Parity Selected, '1'=Odd Parity Selected
--      ParityStick : '0'=Stick Parity Disable, '1'=Stick Parity Enable
--
--    <Receiver/Transmitter status>
--      RxRDY       : RBR data is ready to be read
--      OverrunErr  : Overrun error
--      ParityErr   : Parity error
--      FrameErr    : Frame error
--      BreakInt    : BREAK interrupt
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.1 :| J.H.              :| 06/19/01  :| Support ispMACH 5000VG
--   V1.0 :| D.W. & J.H.       :| 06/01/01  :| First Release
-- --------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Unsigned.all;

entity Rxcver is
  port (
    -- Global reset and clock
    Reset       : in  std_logic; -- Master reset
    Clk16X      : in  std_logic; -- UART internal clock
    -- Register
    RBR         : out std_logic_vector(7 downto 0); -- Receiver Buffer Reg
    -- Rising edge of RBR, LSR read strobes
    RbrRDn_re   : in  std_logic; -- pulse indicating rising of RbrRDn_r
    LsrRDn_re   : in  std_logic; -- pulse indicating rising of LsrRDn_r
    -- Receiver input
    SIN         : in  std_logic;
    -- Receiver control
    Databits    : in  std_logic_vector(1 downto 0); -- Data bits length
    ParityEnable: in  std_logic; -- 0= Parity Disabled; 1= Parity Enabled
    ParityEven  : in  std_logic; -- 0= Odd Parity; 1= Even Parity
    ParityStick : in  std_logic; -- 0= Stick Disabled; 1= Stick Enabled
    -- Receiver status
    RxRDY       : out std_logic; -- Receiver data ready to read
    OverrunErr  : out std_logic; -- Receiver overrun error flag
    ParityErr   : out std_logic; -- Receiver parity error flag
    FrameErr    : out std_logic; -- Receiver framing error flag
    BreakInt    : out std_logic  -- Receiver BREAK interrupt flag
  );
end Rxcver;

architecture Rxcver_a of Rxcver is

  signal NumDataBitReceived_r : std_logic_vector(3 downto 0);

  signal RSR         : std_logic_vector(7 downto 0);
  signal RxPrtyErr   : std_logic;
  signal RxFrmErr    : std_logic;
  signal RxIdle_r    : std_logic;
  signal RbrDataRDY  : std_logic;
  signal CNT_r       : std_logic_vector(3 downto 0);

  signal Hunt_r      : boolean;
  signal HuntOne_r   : std_logic;

  signal SIN1_r      : std_logic;
  signal RxFrmErr1_r : std_logic;
  signal RxIdle1_r   : std_logic;

  signal OverrunErr_r: std_logic;
  signal ParityErr_r : std_logic;
  signal FrameErr_r  : std_logic;
  signal BreakInt_r  : std_logic;

  signal SampledOnce : std_logic;

  -- Receiver Clock Enable Signal
  signal RxClkEn     : std_logic;

  signal RBR_r       : std_logic_vector(7 downto 0);

  -- State Machine Definition
  type state_typ is (idle, shift, parity, stop);
  signal Rx_State : state_typ;

  -- Attributes for ispMACH5000VG to get higher performance
  --   These can be removed when the UART design is targeted to other devices.
  ATTRIBUTE SYN_KEEP : integer;
  ATTRIBUTE SYN_KEEP OF RxPrtyErr, NumDataBitReceived_r, RSR : SIGNAL IS 1;
  ATTRIBUTE SYN_KEEP OF Hunt_r, HuntOne_r, ParityErr_r, FrameErr_r : SIGNAL IS 1;
  ATTRIBUTE SYN_KEEP OF BreakInt_r, RBR_r, OverrunErr_r, RbrDataRDY : SIGNAL IS 1;
  ATTRIBUTE SYN_KEEP OF RxFrmErr, RxIdle_r : SIGNAL IS 1;
  ATTRIBUTE OPT : string;
  ATTRIBUTE OPT OF RxPrtyErr, NumDataBitReceived_r, RSR : SIGNAL IS "KEEP";
  ATTRIBUTE OPT OF Hunt_r, HuntOne_r, ParityErr_r, FrameErr_r : SIGNAL IS "KEEP";
  ATTRIBUTE OPT OF BreakInt_r, RBR_r, OverrunErr_r, RbrDataRDY : SIGNAL IS "KEEP";
  ATTRIBUTE OPT OF RxFrmErr, RxIdle_r : SIGNAL IS "KEEP";

begin

--------------------------------------------------------------------------------
-- Generate RxClkEn signal
--------------------------------------------------------------------------------

  -- RxClkEn : serial port data receiving clock enable
  RxCLK_Proc: process (Reset, Clk16X)
  begin
    if (Reset='1') then
      RxClkEn <= '0';
    elsif rising_edge(Clk16X) then
      if (CNT_r="0110") then
        RxClkEn <= '1';
      else
        RxClkEn <= '0';
      end if;
    end if;
  end process RxCLK_Proc;

  -- CNT_r : 4-bit counter for RxClkEn waveform generation
  CNT_Proc: process (Reset, Clk16X)
  begin
    if (Reset='1') then
      CNT_r <= (others => '0');
    elsif rising_edge(Clk16X) then
      if (Rx_State /= idle) or (Hunt_r) then
        -- Increment count when not idle or when Hunt_r is TRUE
        CNT_r <= CNT_r + 1;
      elsif (SampledOnce='1') then
        -- Adjust 2 clks forward for RxClkEn during the resync after framing error
        CNT_r <= "0010";
      else
        CNT_r <= (others => '0');
      end if;
    end if;
  end process CNT_Proc;

--------------------------------------------------------------------------------
-- Generate Hunt_r
--------------------------------------------------------------------------------

  -- Hunt_r : will be TRUE when start bit is found
  Hunt_r_Proc: process (Reset, Clk16X)
  begin
    if (Reset='1') then
      Hunt_r <= FALSE;
    elsif rising_edge(Clk16X) then
      if (Rx_State=idle) and (SIN='0') and (SIN1_r='1') then
        -- Set Hunt_r when SIN falling edge is found at the idle state
        Hunt_r <= TRUE;
      elsif (SampledOnce='1') and (SIN='0') then
        -- Start bit is successfully sampled twice after framing error
        -- set Hunt_r "true" for resynchronizing of next frame
        Hunt_r <= TRUE;
      elsif (RxIdle_r='0') or (SIN='1') then
        -- Clear Hunt_r when data shifting starts or when SIN returns to '1'
        Hunt_r <= FALSE;
      end if;
    end if;
  end process Hunt_r_Proc;

  -- HuntOne_r :
  --   HuntOne_r, used for BI flag generation, indicates that there is at
  --   least a '1' in the (data + parity + stop) bits of the frame.
  --   Break Interrupt flag(BI) is set to '1' whenever the received input
  --   is held at the '0' state for all bits in the frame (Start bit +
  --   Data bits + Parity bit + Stop bit).  So, as long as HuntOne_r is still
  --   low after all bits are received, BI will be set to '1'.
  HuntOne_r_Proc: process(Clk16X, Reset)
  begin
    if (Reset='1') then
      HuntOne_r <= '0';
    elsif rising_edge(Clk16X) then
      if (Hunt_r) then
        HuntOne_r <= '0';
      elsif (RxIdle_r='0') and (CNT_r(3)='1') and (SIN='1') then
        HuntOne_r <= '1';
      end if;
    end if;