library verilog;use verilog.vl_types.all;entity leg_mem is    port(        i_cache_data    : out    vl_logic_vector(31 downto 0);        d_cache_data    : out    vl_logic_vector(31 downto 0);        i_addr          : in     vl_logic_vector(31 downto 0);        d_addr          : in     vl_logic_vector(31 downto 0);        i_read          : in     vl_logic;        d_dataout       : in     vl_logic_vector(31 downto 0);        d_re            : in     vl_logic;        d_we            : in     vl_logic;        clk             : in     vl_logic;        rst             : in     vl_logic    );end leg_mem;