--   --           _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/--         _/                   _/  ____________________________________________ --         _/                  _/  /                                           / --         _/_/               _/  /                                NAND01GR3B / --          _/_/_/           _/  /                                           /  --             _/_/         _/  /                                     1Gbit / --              _/_/       _/  /        8 bit, 2112 Byte Page, 1.8 V, NAND / --                _/      _/  /                                           / --                _/     _/  /                     VHDL Behavioral Model / --                _/    _/  /                               Version 3.0 / --             _/_/    _/  /                                           /--          _/_/_/    _/  /     Copyright (c) 2006 STMicroelectronics / --        _/_/_/     _/  /___________________________________________/ --  _/_/_/_/_/      _/    --  ----------------------------------------------------------------------------------------------                     STIMULI OPERATIONS FOR NANDxB--              --                            --                                                          ST Microelectronics------------------------------------------------------------------------------------------------------------------------------  LIBRARIES ------------------------------------------------------LIBRARY IEEE;Use  IEEE.std_logic_1164.all;LIBRARY work;Use work.data.all;Use work.TimingData.all;Use work.UserData.all;use ieee.std_logic_arith.all;-------------------------------------- ENTITY DECLARATION --------------------------------------------Entity Stimuli isport      (      I_O : out IObus_type;      E_N, R_N, W_N, WP_N, PRL : out std_logic;      AL, CL: out std_logic;      RB_N : in std_logic;      Vss, Vdd: out real     );End Stimuli;--------------------------------------------------------------------------------------------------------------- ARCHITECTURE -------------------------------------------------------------------------------------------------------------------------------Architecture behavior of Stimuli is-- signals for read signal generation signal CK : std_logic := '1';signal read_cycle : boolean := false;-- signals for address inputsubtype hex_address is std_logic_vector(31 downto 0);constant zero : std_logic_vector(7 downto 0) := (others => '0');constant high_imp : IObus_type := (others => 'Z');-- read signal periodconstant PERIOD: time:= 60 ns; --constant patt_len : integer := 20;begin-- Read signal generator---- When read_cycle=true R_N toggle with T=PERIOD, starting---- with 1 value; when read_cycle goes down R_N goes immediately---- to 1RN_toggle: process(CK, read_cycle) begin   if read_cycle then      CK <= not CK after PERIOD/2;   else      CK <= '1';   end if;end process;R_N <= CK ;---------------------------------  Stimuli generator ----------------------------------------Main : process-- variables for address inputvariable A1, A2, A3, A4, A5: IObus_type;------------------------------------- Procedures used in the process------------------------------------- init deviceprocedure init isbegin  if (CD.Vddmin_dev=Vddmin_R) then      Vdd <= 1.8;  elsif (CD.Vddmin_dev=Vddmin_W) then   Vdd <= 3.0;   end if;  E_N <='1';  W_N <='1'; AL <='0'; CL <='0';   WP_N <='1'; PRL <='1';  I_O <= high_imp;    wait for 5000 ns;  E_N <='0';  wait for 100 ns;end;        -- command inputprocedure insert_command (D: in IObus_type_ext) isvariable D_int : IObus_type := D(IObus_range); begin   I_O <= (others => 'Z'); wait for 5 ns;   CL<='1'; W_N<='0';   I_O <= D_int; wait for 25 ns;          W_N<='1'; wait for 10 ns;           CL<='0'; wait for 10 ns;   I_O <= (others => 'Z'); wait for 10 ns;end;-- data input cycleprocedure insert_data (D: in IObus_type_ext) isvariable D_int : IObus_type := D(IObus_range);begin   I_O <= (others => 'Z'); wait for 5 ns;   CL<='0'; W_N<='0';     I_O <= D_int ; wait for 25 ns;                      W_N<='1'; wait for 10 ns;                      I_O <= (others => 'Z'); wait for 10 ns;  end;-- incremental data pattern input procedure insert_pattern(length : in integer) isbegin   for k in 1 to length loop           I_O <= (others => 'Z'); wait for 10 ns;           CL<='0'; W_N<='0';             I_O <= conv_std_logic_vector(k,IOBusWidth) ; wait for 30 ns;                              W_N<='1'; wait for 20 ns;                      end loop ;    I_O <= (others => 'Z'); wait for 10 ns;end;-- address input cycles procedure insert_address (A: in hex_address) isbegin      if (CD.bus_dev=bus8) then       A1 := A(7 downto 0);       A2 := "0000" & A(11 downto 8);       A3 := A(19 downto 12);       if (CD.size_dev=s_512M) then     A4 := '0' & A(26 downto 20);              elsif (CD.size_dev=s_1G) then    A4 := A(27 downto 20);                     elsif (CD.size_dev=s_2G) then    A4 := A(27 downto 20);      A5 := "0000000" & A(28);       elsif (CD.size_dev=s_4G) then    A4 := A(27 downto 20);      A5 := "000000" & A(29 downto 28);       elsif (CD.size_dev=s_8G) then    A4 := A(27 downto 20);      A5 := "00000" & A(30 downto 28);       end if;          elsif (CD.bus_dev=bus16) then       A1 := zero &  A(7 downto 0);       A2 := zero & "00000" & A(10 downto 8);       A3 := zero & A(18 downto 11);       if (CD.size_dev=s_512M) then     A4 := zero & '0' & A(25 downto 19);               elsif (CD.size_dev=s_1G) then    A4 := zero & A(26 downto 19);                     elsif (CD.size_dev=s_2G) then    A4 := zero & A(26 downto 19);      A5 := zero & "0000000" & A(27);       elsif (CD.size_dev=s_4G) then    A4 := zero & A(26 downto 19);      A5 := zero & "000000" & A(28 downto 27);       elsif (CD.size_dev=s_8G) then    A4 := zero & A(26 downto 19);      A5 := zero & "00000" & A(29 downto 27);       end if;   end if;         CL <='0'; AL <='1'; wait for 5 ns;   I_O <= high_imp; wait for 5 ns;                              I_O <= A1; wait for 25 ns;   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;                   I_O <= A2; wait for 25 ns;    W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;                              I_O <= A3; wait for 25 ns;   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;   I_O <= A4; wait for 25 ns;   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;   if (CD.size_dev >= s_2G) then       I_O <= A5; wait for 25 ns;       W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;   end if;           I_O <= high_imp; wait for 15 ns;    AL<='0'; wait for 5 ns;       end; -- two address cycle (column address)  procedure insert_colAddress (A: in hex_address) isbegin   if (CD.bus_dev=bus8) then       A1 := A(7 downto 0);       A2 := "0000" & A(11 downto 8);   elsif (CD.bus_dev=bus16) then       A1 := zero & A(7 downto 0);       A2 := zero & "00000" & A(10 downto 8);   end if;      CL <='0'; AL <='1'; wait for 5 ns;   I_O <= high_imp; wait for 5 ns;                              I_O <= A1; wait for 25 ns;   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;                   I_O <= A2; wait for 25 ns;    W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;   I_O <= high_imp; wait for 15 ns;    AL<='0'; wait for 5 ns;end; -- insert block address  procedure insert_blockAddress (A: in hex_address) isbegin   if (CD.bus_dev=bus8) then       A3 := A(19 downto 12);       if (CD.size_dev=s_512M) then     A4 := '0' & A(26 downto 20);              elsif (CD.size_dev=s_1G) then    A4 := A(27 downto 20);                     elsif (CD.size_dev=s_2G) then    A4 := A(27 downto 20);      A5 := "0000000" & A(28);       elsif (CD.size_dev=s_4G) then    A4 := A(27 downto 20);      A5 := "000000" & A(29 downto 28);       elsif (CD.size_dev=s_8G) then    A4 := A(27 downto 20);      A5 := "00000" & A(30 downto 28);       end if;          elsif (CD.bus_dev=bus16) then       A3 := zero & A(18 downto 11);       if (CD.size_dev=s_512M) then     A4 := zero & '0' & A(25 downto 19);               elsif (CD.size_dev=s_1G) then    A4 := zero & A(26 downto 19);                     elsif (CD.size_dev=s_2G) then    A4 := zero & A(26 downto 19);      A5 := zero & "0000000" & A(27);       elsif (CD.size_dev=s_4G) then    A4 := zero & A(26 downto 19);      A5 := zero & "000000" & A(28 downto 27);       elsif (CD.size_dev=s_8G) then    A4 := zero & A(26 downto 19);      A5 := zero & "00000" & A(29 downto 27);       end if;   end if;   CL <='0'; AL <='1'; wait for 5 ns;   I_O <= high_imp; wait for 5 ns;                              I_O <= A3; wait for 25 ns;   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;                   I_O <= A4; wait for 25 ns;    W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;   if (CD.size_dev >= s_2G) then       I_O <= A5; wait for 25 ns;       W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;   end if;   I_O <= high_imp; wait for 15 ns;    AL<='0'; wait for 5 ns;end;   -- bus read operation (n = number of memory location to be read)procedure BusRead_op (n : in integer)  isbegin   read_cycle <= true;   wait for n*PERIOD ;       read_cycle <= false;   wait for 100 ns;end;-- end stimuliprocedure end_stim isbegin   E_N<='1';   wait for 1000 ns;   assert (false) report "End Of Stimuli" severity(warning);   wait;end;-- address to be programmedvariable addr1, addr2 : hex_address ; -- block 0 / last page----------------------------------------------- Begin process for stimuli generation--------------------------------------------begin  init;addr1 := x"032003F0";addr2 := x"033004F0";-- read block lock status of locked blocks (expected status = 0002)insert_command(x"007A");insert_blockAddress(addr1);BusRead_op(1);insert_command(x"007A");insert_blockAddress(addr2);BusRead_op(1);-- unlock block intervalinsert_command(x"0023");insert_blockAddress(addr1);insert_command(x"0024");insert_blockAddress(addr2);-- read block lock status of unlocked blocks (expected status = 0006)insert_command(x"007A");insert_blockAddress(addr1);BusRead_op(1);insert_command(x"007A");insert_blockAddress(addr2);BusRead_op(1);-- lock all blocks (lock command)insert_command(x"002A");-- read block lock status of ex-unlocked blocks, now locked (expected status = 0002) insert_command(x"007A");insert_blockAddress(addr1);BusRead_op(1);-- end stimuliend_stim;end process;end behavior;