Release 8.1i par I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.ZHW::  Thu Mar 22 16:25:47 2007par -w -intstyle ise -ol high -t 1 ddr_cntl_a_map.ncd ddr_cntl_a.ncd
ddr_cntl_a.pcf Constraints file: ddr_cntl_a.pcf.Loading device for application Rf_Device from file '3s4000.nph' in environment D:\hardware\Xilinx.   "ddr_cntl_a" is an NCD, version 3.1, device xc3s4000, package fg900, speed -5Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)INFO:Timing:2802 - Read 274 constraints.  If you are experiencing memory or runtime issues it may help to consolidate
   some of these constraints.  For more details please see solution 10784 at support.xilinx.comDevice speed data version:  "PRODUCTION 1.37 2005-11-04".INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.Device Utilization Summary:   Number of BUFGMUXs                  2 out of 8      25%   Number of DCMs                      1 out of 4      25%   Number of External IOBs            70 out of 633    11%      Number of LOCed IOBs            70 out of 70    100%   Number of Slices                  774 out of 27648   2%      Number of SLICEMs              194 out of 13824   1%   Number of LOCed Slices            124 out of 774    16%      Number of LOCed SLICEMs         82 out of 194    42%Overall effort level (-ol):   High Router effort level (-rl):    High Starting initial Timing Analysis.  REAL time: 10 secs Finished initial Timing Analysis.  REAL time: 10 secs WARNING:Par:276 - The signal SYS_CLKb_IBUF has no loadStarting RouterPhase 1: 5038 unrouted;       REAL time: 11 secs Phase 2: 3716 unrouted;       REAL time: 14 secs Phase 3: 787 unrouted;       REAL time: 16 secs Phase 4: 787 unrouted; (185580)      REAL time: 16 secs Phase 5: 835 unrouted; (178273)      REAL time: 17 secs Phase 6: 835 unrouted; (178273)      REAL time: 17 secs Phase 7: 0 unrouted; (179125)      REAL time: 19 secs Phase 8: 0 unrouted; (179125)      REAL time: 20 secs Phase 9: 0 unrouted; (160565)      REAL time: 8 mins 16 secs WARNING:Route:447 - CLK Net:clk_0 may have excessive skew because    33 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs3_delayed_col1 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs2_delayed_col0 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs1_delayed_col1 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs0_delayed_col0 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs2_delayed_col1 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs0_delayed_col1 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs3_delayed_col0 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/dqs1_delayed_col0 may have excessive skew because    2 NON-CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col0_n may have excessive skew
   because    2 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs3_delayed_col0_n may have excessive skew because    4 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs3_delayed_col1_n may have excessive skew because    4 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs2_delayed_col1_n may have excessive skew because    4 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs1_delayed_col0_n may have excessive skew because    4 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs1_delayed_col1_n may have excessive skew because    4 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs0_delayed_col0_n may have excessive skew because    4 CLK pins failed to route using a CLK template.WARNING:Route:447 - CLK Net:main_00/top0/data_path0/data_read0/dqs0_delayed_col1_n may have excessive skew because    4 CLK pins failed to route using a CLK template.Total REAL time to Router completion: 8 mins 16 secs Total CPU time to Router completion: 8 mins 16 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|             clk90_0 |      BUFGMUX6| No   |  402 |  0.623     |  1.432      |+---------------------+--------------+------+------+------------+-------------+|               clk_0 |      BUFGMUX7| No   |  301 |  0.574     |  1.400      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs3_delayed_col |              |      |      |            |             ||                   1 |         Local|      |    8 |  0.012     |  0.502      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs2_delayed_col |              |      |      |            |             ||                   0 |         Local|      |    7 |  0.013     |  0.460      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs1_delayed_col |              |      |      |            |             ||                   1 |         Local|      |    8 |  0.009     |  0.490      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs0_delayed_col |              |      |      |            |             ||                   0 |         Local|      |    7 |  0.020     |  0.516      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs2_delayed_col |              |      |      |            |             ||                   1 |         Local|      |    8 |  0.018     |  0.493      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs0_delayed_col |              |      |      |            |             ||                   1 |         Local|      |    8 |  0.032     |  0.485      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs3_delayed_col |              |      |      |            |             ||                   0 |         Local|      |    7 |  0.008     |  0.497      |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa |              |      |      |            |             ||th0/dqs1_delayed_col |              |      |      |            |             ||                   0 |         Local|      |    7 |  0.004     |  0.494      |+---------------------+--------------+------+------+------------+-------------+