<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
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<messages>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs3_delayed_col1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs2_delayed_col0 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs1_delayed_col1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs0_delayed_col0 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs2_delayed_col1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs0_delayed_col1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs3_delayed_col0 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs1_delayed_col0 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs3_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs1_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs0_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs3_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs1_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read_controller0/dqs0_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs3_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs3_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs2_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs2_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs1_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs1_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs0_delayed_col0_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/data_read0/dqs0_delayed_col1_n is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/ddr1_test_bench0/_n0003 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;GLOBAL_LOGIC1&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;SYS_CLKb_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="767">Unexpected DCM configuration. The signal on the CLKIN pin of DCM comp infrastructure_top0/clk_dcm0/infrastructure_top0/clk_dcm0/DCM_INST1 is not driven by an IOB or BUFGMUX therefore the phase relationship of output clocks to CLKIN cannot be guaranteed.
</msg>

<msg type="warning" file="PhysDesignRules" num="739">Unexpected DCM feedback loop. The signal infrastructure_top0/clk_dcm0/clk on the CLKFB pin of comp infrastructure_top0/clk_dcm0/infrastructure_top0/clk_dcm0/DCM_INST1 is not driven by an IOB or BUFGMUX therefore the phase relationship of output clocks to CLKIN cannot be guaranteed.
</msg>

</messages>