Release 8.1i Map I.24Xilinx Mapping Report File for Design 'ddr_cntl_a'Design Information------------------Command Line   : D:\hardware\Xilinx\bin\nt\map.exe -ise
E:/hardware/KDVM26402/fpga/ddr_cntl_a_withtb/ddr_cntl_a_withtb.ise -intstyle ise
-p xc3s4000-fg900-5 -timing -logic_opt off -ol high -t 1 -cm area -pr b -k 4 -o
ddr_cntl_a_map.ncd ddr_cntl_a.ngd ddr_cntl_a.pcf Target Device  : xc3s4000Target Package : fg900Target Speed   : -5Mapper Version : spartan3 -- $Revision: 1.34 $Mapped Date    : Thu Mar 22 16:24:41 2007Design Summary--------------Number of errors:      0Number of warnings:   35Logic Utilization:  Number of Slice Flip Flops:         767 out of  55,296    1%  Number of 4 input LUTs:             543 out of  55,296    1%Logic Distribution:  Number of occupied Slices:                          774 out of  27,648    2%    Number of Slices containing only related logic:     774 out of     774  100%    Number of Slices containing unrelated logic:          0 out of     774    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:            794 out of  55,296    1%  Number used as logic:                543  Number used as a route-thru:          15  Number used for Dual Port RAMs:      128    (Two LUTs used per Dual Port RAM)  Number used as Shift registers:      108  Number of bonded IOBs:               70 out of     633   11%    IOB Flip Flops:                    52    IOB Dual-Data Rate Flops:          44  Number of GCLKs:                     2 out of       8   25%  Number of DCMs:                      1 out of       4   25%Total equivalent gate count for design:  33,014Additional JTAG gate count for IOBs:  3,360Peak Memory Usage:  261 MBTable of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network SYS_CLKb_IBUF has no load.WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 83
   more times for the following (max. 5 shown):   infrastructure_top0/delay_sel_val1_val_tb<4>,   infrastructure_top0/delay_sel_val1_val_tb<1>,   infrastructure_top0/delay_sel_val1_val_tb<0>,   main_00/ar_done_val1,   main_00/u1_config_parms<9>   To see the details of these warning messages, please use the -detail switch.WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "infrastructure_top0/clk_dcm0/BUFG_CLK0/physical_group_O/u1" (output
   signal=clk_0) has a mix of clock and non-clock loads. Some of the non-clock
   loads are (maximum of 5 listed):   Pin I0 of main_00/ddr1_test_bench0/_n00031   Pin D of infrastructure_top0/cal_top0/tap_dly0/r0   Pin D of infrastructure_top0/cal_top0/tap_dly0/r1   Pin D of infrastructure_top0/cal_top0/tap_dly0/r2   Pin D of infrastructure_top0/cal_top0/tap_dly0/r3WARNING:Pack:1236 - The register main_00/top0/controller0/rst_iob_out has the
   property IOB=TRUE, but failed to join the output side of an I/O component.
   Symbol main_00/top0/controller0/rst_iob_out is not under the same hierarchy
   region as symbol main_00/top0/iobs0/controller_iobs0/rst_iob_outbuf. There
   are three ways to fix the problem:   1. Put both symbols under the same hierarchy region and process the design.
   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
   code I/O registers on the top level of code. If this can not be done, it is
   suggested to instantiate the proper I/O buffer in the lower level of code and
   disable I/O buffer inference for that port in the design.   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
   main_00/top0/controller0 and main_00/top0/iobs0/controller_iobs0 in the UCF
   file.   3. Run map with the option -ignore_keep_hierarchy. This option will dissolve
   all hierarchy in the design.WARNING:Pack:1237 - The register main_00/top0/controller0/rst_iob_out failed to
   join the output side of an I/O component. Symbol
   main_00/top0/controller0/rst_iob_out is not under the same hierarchy region
   as symbol main_00/top0/iobs0/controller_iobs0/rst_iob_outbuf. There are three
   ways to fix the problem:   1. Put both symbols under the same hierarchy region and process the design.
   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
   code I/O registers on the top level of code. If this can not be done, it is
   suggested to instantiate the proper I/O buffer in the lower level of code and
   disable I/O buffer inference for that port in the design.   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
   main_00/top0/controller0 and main_00/top0/iobs0/controller_iobs0 in the UCF
   file.   3. Run map with the option -ignore_keep_hierarchy. This option will dissolve
   all hierarchy in the design.WARNING:Pack:1237 - The register main_00/ddr1_test_bench0/INST3/led_state failed
   to join the output side of an I/O component. Symbol
   main_00/ddr1_test_bench0/INST3/led_state is not under the same hierarchy
   region as symbol cntrl0_led_error_output1_OBUF. There are three ways to fix
   the problem:   1. Put both symbols under the same hierarchy region and process the design.
   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
   code I/O registers on the top level of code. If this can not be done, it is
   suggested to instantiate the proper I/O buffer in the lower level of code and
   disable I/O buffer inference for that port in the design.   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
   main_00/ddr1_test_bench0/INST3 in the UCF file.   3. Run map with the option -ignore_keep_hierarchy. This option will dissolve
   all hierarchy in the design.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs3_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs2_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs1_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs0_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs2_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs0_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs3_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs1_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs3_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs1_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs0_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net