?? ddr_cntl_a_map.mrp
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Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| SYS_CLK | IOB | INPUT | LVCMOS33 | | | | | || SYS_CLKb | IOB | INPUT | LVCMOS33 | | | | | || cntrl0_DDR_A<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<4> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<5> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<6> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<7> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<8> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<9> | IOB | OUTPUT | SSTL2_II | | | | | || cntrl0_DDR_A<10> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_A<11> | IOB | OUTPUT | SSTL2_II | | | | | || cntrl0_DDR_A<12> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_BA<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_BA<1> | IOB | OUTPUT | SSTL2_II | | | | | || cntrl0_DDR_CAS_N | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_CK<0> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_CK<1> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_CKE | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_CK_N<0> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_CK_N<1> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_CS_N | IOB | OUTPUT | SSTL2_II | | | | | || cntrl0_DDR_DM<0> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_DM<1> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_DM<2> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_DM<3> | IOB | OUTPUT | SSTL2_II | | | OUTDDR | | || cntrl0_DDR_DQ<0> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<1> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<2> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<3> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<4> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<5> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<6> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<7> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<8> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<9> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<10> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<11> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<12> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<13> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<14> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<15> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<16> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<17> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<18> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<19> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<20> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<21> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<22> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<23> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<24> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<25> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<26> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<27> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<28> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<29> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<30> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQ<31> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF1 | | || cntrl0_DDR_DQS<0> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF2 | | || cntrl0_DDR_DQS<1> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF2 | | || cntrl0_DDR_DQS<2> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF2 | | || cntrl0_DDR_DQS<3> | IOB | BIDIR | SSTL2_II | | | OUTDDR | | || | | | | | | ENFF2 | | || cntrl0_DDR_RAS_N | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_DDR_WE_N | IOB | OUTPUT | SSTL2_II | | | OFF1 | | || cntrl0_led_error_output1 | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | || cntrl0_rst_dqs_div_in | IOB | INPUT | SSTL2_II | | | | | || cntrl0_rst_dqs_div_out | IOB | OUTPUT | SSTL2_II | | | | | || reset_in | IOB | INPUT | LVCMOS33 | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------infrastructure_top0/cal_top0/tap_dly0/l0Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------Number of Timing Constraints that were not applied: 27Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in1" MAXD | 0.700ns | 3.953ns | 0 | -3.253ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in2" MAXD | 0.700ns | 3.953ns | 0 | -3.253ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in3" MAXD | 0.700ns | 3.953ns | 0 | -3.253ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in0" MAXD | 0.700ns | 3.953ns | 0 | -3.253ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* TS_infrastructure_top0_clk_dcm0_clk0dcm = | 7.518ns | 8.660ns | 1 | -1.142ns | 1 PERIOD TIMEGRP "infrastructure_top0_clk_ | | | | | dcm0_clk0dcm" TS_SYS_CLK HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/data_path0/data_read_co | 0.160ns | 0.371ns | 0 | -0.211ns | 1 ntroller0/dqs_delay3_col1/delay1" MAXDELA | | | | | Y = 0.16 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/data_path0/data_read_co | 0.160ns | 0.371ns | 0 | -0.211ns | 1 ntroller0/dqs_delay3_col0/delay1" MAXDELA | | | | | Y = 0.16 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/data_path0/data_read_co | 0.160ns | 0.371ns | 0 | -0.211ns | 1 ntroller0/dqs_delay2_col1/delay1" MAXDELA | | | | | Y = 0.16 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/data_path0/data_read_co | 0.160ns | 0.371ns | 0 | -0.211ns | 1 ntroller0/dqs_delay2_col0/delay1" MAXDELA | | | | | Y = 0.16 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/data_path0/data_read_co | 0.160ns | 0.371ns | 0 | -0.211ns | 1 ntroller0/dqs_delay1_col1/delay1" MAXDELA | | | | | Y = 0.16 ns | | | | | ?? 快捷鍵說明
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