//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_data_path_rst.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: This module contains the FD instantiations for various reset signals///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100psmodule ddr_cntl_a_data_path_rst( clk90,                      clk,                      reset,                      reset90,                      reset180,                      reset270,                      reset_r,                      reset90_r,                      reset90_r1,                      reset180_r,                      reset270_r );   input clk90;   input reset;   input reset90;   input reset180;   input reset270;   input clk;    output reset_r;   output reset90_r;   output reset90_r1;   output reset180_r;   output reset270_r;      FD rst0_r (.Q(reset_r), .C(clk),. D(reset));  FD rst90_r (.Q(reset90_r), .C(clk90),. D(reset90));  FD rst90_r1 (.Q(reset90_r1), .C(clk90),. D(reset90));  FD rst180_r (.Q(reset180_r), .C(~clk),. D(reset180));  FD rst270_r (.Q(reset270_r), .C(~clk90),. D(reset270));                      endmodule