//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_data_write_0.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: Data write operation performed through the pipelines in this module.///////////////////////////////////////////////////////////////////////////////  `timescale 1ns/100ps`include "ddr_cntl_a_parameters_0.v"module    ddr_cntl_a_data_write_0	(      user_input_data,    	user_data_mask,     clk90,       reset90_r,               reset270_r,              write_enable,            write_en_val,            write_data_falling,      write_data_rising,       data_mask_f,     data_mask_r     );input     [((`data_width*2)-1):0]user_input_data;input     [((`data_mask_width*2)-1):0] user_data_mask;input     clk90;            input     reset90_r;          input     reset270_r;         input     write_enable;       output    write_en_val;       output    [((`data_width)-1):0]write_data_falling; output    [((`data_width)-1):0]write_data_rising;  output    [((`data_mask_width)-1):0]data_mask_f;        output    [((`data_mask_width)-1):0]data_mask_r;   reg write_en_val;reg write_en_P1;          reg write_en_P2;          reg write_en_P3;          reg write_en_int;         reg [((`data_width*2)-1):0]write_data;    reg [((`data_width*2)-1):0]write_data1;   reg [((`data_width*2)-1):0]write_data2;   reg [((`data_width*2)-1):0]write_data3;   reg [((`data_width*2)-1):0]write_data4;  reg [((`data_width*2)-1):0]write_data_reg_dimm;       //Added for Registered Dimms reg [((`data_width*2)-1):0]write_data270;   wire [((`data_width*2)-1):0]write_data0;reg [((`data_width)-1):0]write_data270_1;reg [((`data_width)-1):0]write_data270_2;reg [((`data_width)-1):0]write_data270_3;              //Added for Registered Dimms wire [((`data_mask_width*2)-1):0] write_data_m0;    reg [((`data_mask_width*2)-1):0] write_data_m1;   reg [((`data_mask_width*2)-1):0] write_data_m2;   reg [((`data_mask_width*2)-1):0] write_data_m3;   reg [((`data_mask_width*2)-1):0] write_data_m4;  reg [((`data_mask_width*2)-1):0] write_data_m270;   reg [((`data_mask_width*2)-1):0] write_data_mask;reg [((`data_mask_width*2)-1):0] write_data_mask_reg_dimm;  //Added for Registered Dimms reg [((`data_mask_width)-1):0] write_data_m270_1;reg [((`data_mask_width)-1):0] write_data_m270_2;reg [((`data_mask_width)-1):0] write_data_m270_3;       //Added for Registered Dimms assign write_data0 = user_input_data;  assign write_data_m0 = user_data_mask;     always@(posedge clk90)begin 	write_data1 <= write_data0;	write_data2 <= write_data1;	write_data3 <= write_data2;	write_data4 <= write_data3;end always@(posedge clk90)begin 	write_data_m1 <= write_data_m0;   	write_data_m2 <= write_data_m1;     	write_data_m3 <= write_data_m2; 	write_data_m4 <= write_data_m3; end always@(posedge clk90)	write_data270 <= write_data4;always@(posedge clk90)	write_data_m270 <= write_data_m4;always@(posedge clk90)begin  	write_data	<= write_data270;      write_data_reg_dimm <= write_data;      //Added for Registered Dimms    end   // pipeline varablesalways@(posedge clk90)begin  	write_data_mask <= write_data_m270;      write_data_mask_reg_dimm <= write_data_mask;   //Added for Registered Dimms  end   // pipeline varablesalways@(negedge clk90)begin	write_data270_1  <= write_data4 [(`data_width*2)-1 : `data_width] ;	write_data270_2 <= write_data270_1; 	write_data270_3 <= write_data270_2;         //Added for Registered Dimms    endalways@(negedge clk90)begin	write_data_m270_1 <= write_data_m4 [(`data_mask_width*2)-1:`data_mask_width];	write_data_m270_2 <= write_data_m270_1; 	write_data_m270_3 <= write_data_m270_2;     //Added for Registered Dimms    end     assign write_data_rising  = write_data270_2;      assign write_data_falling = write_data[(`data_width-1):0];       assign data_mask_r = write_data_m270_2;                   assign data_mask_f = write_data_mask[(`data_mask_width-1):0];    // data path for write enablealways@(posedge clk90)begin        write_en_P1 <= write_enable;        write_en_P2 <= write_en_P1;        write_en_P3 <= write_en_P2;endalways@(negedge clk90)begin     	write_en_int   <= write_en_P2;//P2     	write_en_val   <= write_en_P1; //int;endendmodule