Release 8.1i - Bitgen I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.Loading device for application Rf_Device from file '3s4000.nph' in environment
D:\hardware\Xilinx.   "ddr_cntl_a" is an NCD, version 3.1, device xc3s4000, package fg900, speed -5Opened constraints file ddr_cntl_a.pcf.Thu Mar 22 16:34:24 2007D:\hardware\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Compress -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullNone -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No ddr_cntl_a.ncd 
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Enabled)            |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 6**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| DCMShutdown          | Disable**            |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired**         |
+----------------------+----------------------+
| CclkPin              | Pullup**             |
+----------------------+----------------------+
| DonePin              | Pullup**             |
+----------------------+----------------------+
| HswapenPin           | Pullup*              |
+----------------------+----------------------+
| M0Pin                | Pullup**             |
+----------------------+----------------------+
| M1Pin                | Pullup**             |
+----------------------+----------------------+
| M2Pin                | Pullup**             |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pullnone             |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| Match_cycle          | Auto*                |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| PartialMask0         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask1         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask2         | (Not Specified)*     |
+----------------------+----------------------+
| PartialGclk          | (Not Specified)*     |
+----------------------+----------------------+
| PartialLeft          | (Not Specified)*     |
+----------------------+----------------------+
| PartialRight         | (Not Specified)*     |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

Running DRC.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs3_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs2_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs1_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs0_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs2_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs0_delayed_col1 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs3_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/dqs1_delayed_col0 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs3_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs1_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs0_delayed_col1_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs3_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs1_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs0_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs3_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs3_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs2_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs2_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs1_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs1_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs0_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs0_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/ddr1_test_bench0/_n0003 is sourced by a combinatorial pin. This is
   not good design practice. Use the CE pin to control the loading of data into
   the flip-flop.WARNING:PhysDesignRules:367 - The signal <GLOBAL_LOGIC1> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <SYS_CLKb_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:767 - Unexpected DCM configuration. The signal on the
   CLKIN pin of DCM comp
   infrastructure_top0/clk_dcm0/infrastructure_top0/clk_dcm0/DCM_INST1 is not
   driven by an IOB or BUFGMUX therefore the phase relationship of output clocks
   to CLKIN cannot be guaranteed.WARNING:PhysDesignRules:739 - Unexpected DCM feedback loop. The signal
   infrastructure_top0/clk_dcm0/clk on the CLKFB pin of comp
   infrastructure_top0/clk_dcm0/infrastructure_top0/clk_dcm0/DCM_INST1 is not
   driven by an IOB or BUFGMUX therefore the phase relationship of output clocks
   to CLKIN cannot be guaranteed.DRC detected 0 errors and 29 warnings.Creating bit map...Saving bit stream in "ddr_cntl_a.bit".Bitstream compression saved 6989344 bits.Bitstream generation is complete.