Release 8.1i - xst I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.01 / 0.41 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.41 s | Elapsed : 0.00 / 1.00 s --> Reading design: ddr_cntl_a.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis     5.1) Advanced HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "ddr_cntl_a.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "ddr_cntl_a"Output Format                      : NGCTarget Device                      : xc3s4000-5-fg900---- Source OptionsTop Module Name                    : ddr_cntl_aAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : YESRTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : ddr_cntl_a.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "ddr_cntl_a_wr_gray_cntr.v" in library workCompiling verilog file "ddr_cntl_a_s3_dqs_iob.v" in library workModule <ddr_cntl_a_wr_gray_cntr> compiledCompiling verilog file "ddr_cntl_a_s3_ddr_iob.v" in library workModule <ddr_cntl_a_s3_dqs_iob> compiledCompiling verilog file "ddr_cntl_a_rd_gray_cntr.v" in library workModule <ddr_cntl_a_s3_ddr_iob> compiledCompiling verilog file "ddr_cntl_a_fifo_1_wr_en_0.v" in library workModule <ddr_cntl_a_rd_gray_cntr> compiledCompiling verilog file "ddr_cntl_a_fifo_0_wr_en_0.v" in library workModule <ddr_cntl_a_fifo_1_wr_en_0> compiledCompiling verilog file "ddr_cntl_a_dqs_delay.v" in library workModule <ddr_cntl_a_fifo_0_wr_en_0> compiledCompiling verilog file "ddr_cntl_a_ddr1_dm_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_dqs_delay> compiledCompiling verilog file "ddr_cntl_a_RAM8D_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_ddr1_dm_0> compiledCompiling verilog file "ddr_cntl_a_infrastructure_iobs_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_RAM8D_0> compiledCompiling verilog file "ddr_cntl_a_data_write_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_infrastructure_iobs_0> compiledCompiling verilog file "ddr_cntl_a_data_read_controller_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_data_write_0> compiledCompiling verilog file "ddr_cntl_a_data_read_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_data_read_controller_0> compiledCompiling verilog file "ddr_cntl_a_data_path_rst.v" in library workModule <ddr_cntl_a_data_read_0> compiledCompiling verilog file "ddr_cntl_a_data_path_iobs_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_data_path_rst> compiledCompiling verilog file "ddr_cntl_a_controller_iobs_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_data_path_iobs_0> compiledCompiling verilog file "ddr_cntl_a_tap_dly_0.v" in library workModule <ddr_cntl_a_controller_iobs_0> compiledCompiling verilog file "ddr_cntl_a_mybufg_0.v" in library workModule <ddr_cntl_a_tap_dly_0> compiledCompiling verilog file "ddr_cntl_a_lfsr32_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_mybufg_0> compiledCompiling verilog file "ddr_cntl_a_iobs_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_lfsr32_0> compiledCompiling verilog file "ddr_cntl_a_infrastructure.v" in library workModule <ddr_cntl_a_iobs_0> compiledCompiling verilog file "ddr_cntl_a_data_path_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_infrastructure> compiledCompiling verilog file "ddr_cntl_a_controller_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_data_path_0> compiledCompiling verilog file "ddr_cntl_a_cmp_data_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_controller_0> compiledCompiling verilog file "ddr_cntl_a_cmd_fsm_0.v" in library workModule <ddr_cntl_a_cmp_data_0> compiledCompiling verilog file "ddr_cntl_a_cal_ctl_0.v" in library workModule <ddr_cntl_a_cmd_fsm_0> compiledCompiling verilog file "ddr_cntl_a_addr_gen_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_cal_ctl_0> compiledCompiling verilog file "ddr_cntl_a_top_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_addr_gen_0> compiledCompiling verilog file "ddr_cntl_a_ddr1_test_bench_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_top_0> compiledCompiling verilog file "ddr_cntl_a_clk_dcm.v" in library workModule <ddr_cntl_a_ddr1_test_bench_0> compiledCompiling verilog file "ddr_cntl_a_cal_top.v" in library workModule <ddr_cntl_a_clk_dcm> compiledCompiling verilog file "ddr_cntl_a_main_0.v" in library workCompiling verilog include file "ddr_cntl_a_parameters_0.v"Module <ddr_cntl_a_cal_top> compiledCompiling verilog file "ddr_cntl_a_infrastructure_top.v" in library workModule <ddr_cntl_a_main_0> compiledCompiling verilog file "ddr_cntl_a.v" in library workModule <ddr_cntl_a_infrastructure_top> compiledModule <ddr_cntl_a> compiledNo errors in compilationAnalysis of file <"ddr_cntl_a.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <ddr_cntl_a>.Module <ddr_cntl_a> is correct for synthesis. Analyzing module <ddr_cntl_a_main_0>.Module <ddr_cntl_a_main_0> is correct for synthesis. Analyzing module <ddr_cntl_a_top_0>.Module <ddr_cntl_a_top_0> is correct for synthesis. Analyzing module <ddr_cntl_a_controller_0>.	IDLE = 4'b0000	PRECHARGE = 4'b0001	LOAD_MODE_REG = 4'b0010	AUTO_REFRESH = 4'b0011	ACTIVE = 4'b0100	FIRST_WRITE = 4'b0101	WRITE_WAIT = 4'b0110	BURST_WRITE = 4'b0111	READ_AFTER_WRITE = 4'b1000	PRECHARGE_AFTER_WRITE = 4'b1001	PRECHARGE_AFTER_WRITE_2 = 4'b1010	READ_WAIT = 4'b1011	BURST_READ = 4'b1100	BURST_STOP = 4'b1101	ACTIVE_WAIT = 4'b1110