Set user-defined property "INIT =  0" for instance <u25> in unit <ddr_cntl_a_tap_dly_0>.    Set user-defined property "INIT =  0" for instance <u26> in unit <ddr_cntl_a_tap_dly_0>.    Set user-defined property "INIT =  0" for instance <u27> in unit <ddr_cntl_a_tap_dly_0>.    Set user-defined property "INIT =  0" for instance <u28> in unit <ddr_cntl_a_tap_dly_0>.    Set user-defined property "INIT =  0" for instance <u29> in unit <ddr_cntl_a_tap_dly_0>.    Set user-defined property "INIT =  0" for instance <u30> in unit <ddr_cntl_a_tap_dly_0>.    Set user-defined property "INIT =  0" for instance <u31> in unit <ddr_cntl_a_tap_dly_0>.=========================================================================*                           HDL Synthesis                               *=========================================================================INFO:Xst:1304 - Contents of register <wrburst_end_9> in unit <ddr_cntl_a_controller_0> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <ddr_cntl_a_tap_dly_0>.    Related source file is "ddr_cntl_a_tap_dly_0.v".    Found 1-bit xor2 for signal <$n0031>.    Found 1-bit xor2 for signal <$n0032>.    Found 1-bit xor2 for signal <$n0033>.    Found 1-bit xor2 for signal <$n0034>.    Found 1-bit xor2 for signal <$n0035>.    Found 1-bit xor2 for signal <$n0036>.    Found 1-bit xor2 for signal <$n0037>.    Found 1-bit xor2 for signal <$n0038>.    Found 1-bit xor2 for signal <$n0039>.    Found 1-bit xor2 for signal <$n0040>.    Found 1-bit xor2 for signal <$n0041>.    Found 1-bit xor2 for signal <$n0042>.    Found 1-bit xor2 for signal <$n0043>.    Found 1-bit xor2 for signal <$n0044>.    Found 1-bit xor2 for signal <$n0045>.    Found 1-bit xor2 for signal <$n0046>.    Found 1-bit xor2 for signal <$n0047>.    Found 1-bit xor2 for signal <$n0048>.    Found 1-bit xor2 for signal <$n0049>.    Found 1-bit xor2 for signal <$n0050>.    Found 1-bit xor2 for signal <$n0051>.    Found 1-bit xor2 for signal <$n0052>.    Found 1-bit xor2 for signal <$n0053>.    Found 1-bit xor2 for signal <$n0054>.    Found 1-bit xor2 for signal <$n0055>.    Found 1-bit xor2 for signal <$n0056>.    Found 1-bit xor2 for signal <$n0057>.    Found 1-bit xor2 for signal <$n0058>.    Found 1-bit xor2 for signal <$n0059>.    Found 1-bit xor2 for signal <$n0060>.    Found 1-bit xor2 for signal <$n0061>.Unit <ddr_cntl_a_tap_dly_0> synthesized.Synthesizing Unit <ddr_cntl_a_cal_ctl_0>.    Related source file is "ddr_cntl_a_cal_ctl_0.v".    Found 4x5-bit ROM for signal <$n0010>.    Found 5-bit register for signal <tapForDqs_tb>.    Found 5-bit register for signal <tapForDqs_rl>.    Found 1-bit 32-to-1 multiplexer for signal <$n0000> created at line 135.    Found 5-bit comparator greater for signal <$n0015> created at line 157.    Found 5-bit comparator less for signal <$n0017> created at line 65.    Found 5-bit comparator greater for signal <$n0019> created at line 155.    Found 5-bit comparator greater for signal <$n0020> created at line 175.    Found 6-bit up counter for signal <cnt>.    Found 6-bit up counter for signal <cnt1>.    Found 1-bit register for signal <enb_trans_two_dtct>.    Found 5-bit up counter for signal <phase_cnt>.    Found 32-bit register for signal <tap_dly_reg>.    Found 1-bit register for signal <trans_oneDtct>.    Found 1-bit register for signal <trans_twoDtct>.    Summary:	inferred   1 ROM(s).	inferred   3 Counter(s).	inferred  35 D-type flip-flop(s).	inferred   4 Comparator(s).	inferred   1 Multiplexer(s).Unit <ddr_cntl_a_cal_ctl_0> synthesized.Synthesizing Unit <ddr_cntl_a_mybufg_0>.    Related source file is "ddr_cntl_a_mybufg_0.v".Unit <ddr_cntl_a_mybufg_0> synthesized.Synthesizing Unit <ddr_cntl_a_cal_top>.    Related source file is "ddr_cntl_a_cal_top.v".    Found 1-bit register for signal <fpga_rst>.    Summary:	inferred   1 D-type flip-flop(s).Unit <ddr_cntl_a_cal_top> synthesized.Synthesizing Unit <ddr_cntl_a_clk_dcm>.    Related source file is "ddr_cntl_a_clk_dcm.v".Unit <ddr_cntl_a_clk_dcm> synthesized.Synthesizing Unit <ddr_cntl_a_lfsr32_0>.    Related source file is "ddr_cntl_a_lfsr32_0.v".    Found 8-bit adder for signal <$n0003> created at line 74.    Found 8-bit register for signal <lfsr_f>.    Found 8-bit up accumulator for signal <lfsr_r>.    Summary:	inferred   1 Accumulator(s).	inferred   1 Adder/Subtractor(s).Unit <ddr_cntl_a_lfsr32_0> synthesized.Synthesizing Unit <ddr_cntl_a_cmp_data_0>.    Related source file is "ddr_cntl_a_cmp_data_0.v".    Found 8-bit comparator not equal for signal <$n0000> created at line 140.    Found 8-bit comparator not equal for signal <$n0001> created at line 137.    Found 8-bit comparator not equal for signal <$n0002> created at line 134.    Found 8-bit comparator not equal for signal <$n0003> created at line 131.    Found 8-bit comparator not equal for signal <$n0004> created at line 141.    Found 8-bit comparator not equal for signal <$n0005> created at line 138.    Found 8-bit comparator not equal for signal <$n0006> created at line 135.    Found 8-bit comparator not equal for signal <$n0007> created at line 132.    Found 4-bit register for signal <byte_err>.    Found 4-bit register for signal <byte_err1>.    Found 1-bit register for signal <led_state>.    Found 64-bit register for signal <read_data_reg>.    Found 1-bit register for signal <val_reg>.    Found 1-bit register for signal <valid>.    Summary:	inferred  75 D-type flip-flop(s).	inferred   8 Comparator(s).Unit <ddr_cntl_a_cmp_data_0> synthesized.Synthesizing Unit <ddr_cntl_a_cmd_fsm_0>.    Related source file is "ddr_cntl_a_cmd_fsm_0.v".WARNING:Xst:647 - Input <rst> is never used.WARNING:Xst:647 - Input <u_data_val> is never used.WARNING:Xst:646 - Signal <current_state> is assigned but never used.WARNING:Xst:646 - Signal <state_bits> is assigned but never used.WARNING:Xst:646 - Signal <num_bursts_max> is assigned but never used.WARNING:Xst:646 - Signal <init_chek> is assigned but never used.INFO:Xst:1799 - State 0100 is never reached in FSM <next_state>.INFO:Xst:1799 - State 0111 is never reached in FSM <next_state>.INFO:Xst:1799 - State 0110 is never reached in FSM <next_state>.INFO:Xst:1799 - State 1001 is never reached in FSM <next_state>.INFO:Xst:1799 - State 1011 is never reached in FSM <next_state>.INFO:Xst:1799 - State 1010 is never reached in FSM <next_state>.    Found finite state machine <FSM_0> for signal <next_state>.    -----------------------------------------------------------------------    | States             | 6                                              |    | Transitions        | 11                                             |    | Inputs             | 6                                              |    | Outputs            | 5                                              |    | Clock              | clk (falling_edge)                             |    | Reset              | $n0000 (positive)                              |    | Reset type         | synchronous                                    |    | Reset State        | 0000                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <r_w>.    Found 1-bit register for signal <addr_inc>.    Found 3-bit register for signal <u_cmd>.    Found 6-bit subtractor for signal <$n0020> created at line 124.    Found 5-bit subtractor for signal <$n0021> created at line 98.    Found 6-bit register for signal <init_dly>.    Found 6-bit 4-to-1 multiplexer for signal <init_dly_p>.    Found 1-bit register for signal <init_done>.    Found 1-bit register for signal <lfsr_rst_180>.    Found 1-bit register for signal <lfsr_rst_90>.    Found 5-bit register for signal <LMD_WAIT_COUNT>.    Found 5-bit 4-to-1 multiplexer for signal <LMD_WAIT_COUNT_value>.    Found 1-bit register for signal <rst_flag>.    Found 1-bit register for signal <temp>.    Summary:	inferred   1 Finite State Machine(s).	inferred  21 D-type flip-flop(s).	inferred   2 Adder/Subtractor(s).	inferred  11 Multiplexer(s).Unit <ddr_cntl_a_cmd_fsm_0> synthesized.Synthesizing Unit <ddr_cntl_a_addr_gen_0>.    Related source file is "ddr_cntl_a_addr_gen_0.v".    Found 1-bit register for signal <cnt_roll>.    Found 1-bit register for signal <burst_done_1_reg>.    Found 1-bit register for signal <burst_done_reg>.    Found 2-bit up counter for signal <cnt>.    Found 1-bit register for signal <cnt_roll_p>.    Found 1-bit register for signal <cnt_roll_p2>.    Found 8-bit up accumulator for signal <column_counter>.    Summary:	inferred   1 Counter(s).	inferred   1 Accumulator(s).	inferred   5 D-type flip-flop(s).Unit <ddr_cntl_a_addr_gen_0> synthesized.Synthesizing Unit <ddr_cntl_a_s3_ddr_iob>.    Related source file is "ddr_cntl_a_s3_ddr_iob.v".WARNING:Xst:1780 - Signal <ddr_dq_o> is never used or assigned.Unit <ddr_cntl_a_s3_ddr_iob> synthesized.Synthesizing Unit <ddr_cntl_a_s3_dqs_iob>.    Related source file is "ddr_cntl_a_s3_dqs_iob.v".Unit <ddr_cntl_a_s3_dqs_iob> synthesized.Synthesizing Unit <ddr_cntl_a_ddr1_dm_0>.    Related source file is "ddr_cntl_a_ddr1_dm_0.v".Unit <ddr_cntl_a_ddr1_dm_0> synthesized.Synthesizing Unit <ddr_cntl_a_data_path_iobs_0>.    Related source file is "ddr_cntl_a_data_path_iobs_0.v".WARNING:Xst:647 - Input <write_en_val1> is never used.Unit <ddr_cntl_a_data_path_iobs_0> synthesized.