//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: glbl.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: ///////////////////////////////////////////////////////////////////////////////// $Header: \projects/mig1.x/mig1.5/tool/mig 1.5_b0.21/data/dlib/spartan3/DDR SDRAM/verilog/rtl/glbl.v,v 1.3 2006/07/11 12:24:06 venkat Exp $`timescale  1 ps / 1 psmodule glbl (GSR,             GTS,             PRLD);                 output GSR, GTS, PRLD;     parameter ROC_WIDTH = 100000;    parameter TOC_WIDTH = 0;    wire GSR;    wire GTS;    wire PRLD;    reg GSR_int;    reg GTS_int;    reg PRLD_int;    assign (weak1, weak0) GSR = GSR_int;    assign (weak1, weak0) GTS = GTS_int;    assign (weak1, weak0) PRLD = PRLD_int;    initial begin	GSR_int = 1'b1;	PRLD_int = 1'b1;	#(ROC_WIDTH)	GSR_int = 1'b0;	PRLD_int = 1'b0;    end    initial begin	GTS_int = 1'b1;	#(TOC_WIDTH)	GTS_int = 1'b0;    endendmodule