?? ddr_cntl_a_iobs_0.v
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//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.6
// \ \ Application : MIG
// / / Filename: ddr_cntl_a_iobs_0.v
// /___/ /\ Date Last Modified: Tue Jul 11 2006
// \ \ / \ Date Created: Mon May 2 2005
// \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module contains the instantiations for
// -infrastructure_iobs,
// -data_path_iobs
// -controller_iobs modules
///////////////////////////////////////////////////////////////////////////////
`include "ddr_cntl_a_parameters_0.v"
`timescale 1ns/100ps
module ddr_cntl_a_iobs_0 (
clk,
clk90,
ddr_rasb_cntrl,
ddr_casb_cntrl,
ddr_web_cntrl,
ddr_cke_cntrl,
ddr_csb_cntrl,
ddr_address_cntrl,
ddr_ba_cntrl,
rst_dqs_div_int,
dqs_reset,
dqs_enable,
ddr_dqs,
ddr_dq,
write_data_falling,
write_data_rising,
write_en_val,
write_en_val1,
reset90_r,
data_mask_f,
data_mask_r,
DDR_CK,
DDR_CK_N,
ddr_rasb,
ddr_casb,
ddr_web,
ddr_ba,
ddr_address,
ddr_cke,
ddr_csb,
rst_dqs_div,
rst_dqs_div_in,
rst_dqs_div_out,
dqs_int_delay_in0,
dqs_int_delay_in1,
dqs_int_delay_in2,
dqs_int_delay_in3,
ddr_dm ,
dq
);
input clk;
input clk90;
//input clk180;
//input clk270;
input ddr_rasb_cntrl;
input ddr_casb_cntrl;
input ddr_web_cntrl;
input ddr_cke_cntrl;
input ddr_csb_cntrl;
input [`row_address-1:0]ddr_address_cntrl;
input [`bank_address-1:0]ddr_ba_cntrl;
input rst_dqs_div_int;
input dqs_reset;
input dqs_enable;
inout [((`data_strobe_width)-1):0]ddr_dqs;
inout [(`data_width-1):0]ddr_dq;
input [(`data_width-1):0]write_data_falling;
input [(`data_width-1):0]write_data_rising;
input write_en_val;
input write_en_val1;
input reset90_r;
input [((`data_mask_width)-1):0]data_mask_f;
input [((`data_mask_width)-1):0]data_mask_r;
output [`clk_width-1:0]DDR_CK;
output [`clk_width-1:0]DDR_CK_N;
output ddr_rasb;
output ddr_casb;
output ddr_web;
output [`bank_address-1:0]ddr_ba;
output [`row_address-1:0]ddr_address;
output ddr_cke;
output ddr_csb;
output rst_dqs_div;
input rst_dqs_div_in;
output rst_dqs_div_out;
output dqs_int_delay_in0;
output dqs_int_delay_in1;
output dqs_int_delay_in2;
output dqs_int_delay_in3;
output [((`data_width)-1):0]dq;
output [((`data_mask_width)-1):0]ddr_dm;
ddr_cntl_a_infrastructure_iobs_0 infrastructure_iobs0 (
.DDR_CK (DDR_CK),
.DDR_CK_N (DDR_CK_N),
.clk0 (clk),
.clk90 (clk90)
);
ddr_cntl_a_controller_iobs_0 controller_iobs0 (
.clk0 (clk),
.ddr_rasb_cntrl (ddr_rasb_cntrl),
.ddr_casb_cntrl (ddr_casb_cntrl),
.ddr_web_cntrl (ddr_web_cntrl),
.ddr_cke_cntrl (ddr_cke_cntrl),
.ddr_csb_cntrl (ddr_csb_cntrl),
.ddr_address_cntrl (ddr_address_cntrl),
.ddr_ba_cntrl (ddr_ba_cntrl),
.rst_dqs_div_int (rst_dqs_div_int),
.ddr_rasb (ddr_rasb),
.ddr_casb (ddr_casb),
.ddr_web (ddr_web),
.ddr_ba (ddr_ba),
.ddr_address (ddr_address),
.ddr_cke (ddr_cke),
.ddr_csb (ddr_csb),
.rst_dqs_div (rst_dqs_div),
.rst_dqs_div_in (rst_dqs_div_in),
.rst_dqs_div_out (rst_dqs_div_out)
);
ddr_cntl_a_data_path_iobs_0 datapath_iobs0 (
.clk (clk),
.clk90 (clk90),
.reset90_r (reset90_r),
.dqs_reset (dqs_reset),
.dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs),
.ddr_dq (ddr_dq),
.write_data_falling (write_data_falling),
.write_data_rising (write_data_rising),
.write_en_val (write_en_val),
.write_en_val1 (write_en_val1),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.ddr_dm (ddr_dm) ,
.ddr_dq_val (dq)
);
endmodule
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