"infrastructure_top0/cal_top0/tap_dly0/r18" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r19" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r20" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r21" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r22" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r23" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r24" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r25" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r26" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r27" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r28" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r29" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r30" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r31" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u0" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u1" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u2" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u3" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u4" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u5" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u6" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u7" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u8" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u9" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u10" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u11" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u12" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u13" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u14" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u15" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u16" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u17" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u18" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u19" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u20" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u21" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u22" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u23" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u24" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u25" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u26" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u27" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u28" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u29" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u30" BEL
        "infrastructure_top0/cal_top0/tap_dly0/u31" BEL
        "infrastructure_top0/wait_200us_1" BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U1" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U2/FF0_pins<0>" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U2/FF1_pins<0>" BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U1" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U2/FF0_pins<0>" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U2/FF1_pins<0>" BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U1" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U2/FF0_pins<0>" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U2/FF1_pins<0>" BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U1" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U2/FF0_pins<0>" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U2/FF1_pins<0>" PIN
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0_INST/FF0_pins<0>" PIN
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0_INST/FF1_pins<0>" PIN
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0B_INST/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0B_INST/FF1_pins<0>"
        PIN "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1_INST/FF0_pins<0>"
        PIN "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1_INST/FF1_pins<0>"
        PIN
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1B_INST/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1B_INST/FF1_pins<0>"
        BEL "main_00/top0/iobs0/controller_iobs0/iob_web" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_rasb" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_casb" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_cke" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr0" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr1" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr2" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr3" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr4" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr5" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr6" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr7" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr8" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr10" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_addr12" BEL
        "main_00/top0/iobs0/controller_iobs0/iob_ba1" BEL
        "main_00/top0/data_path0/data_path_rst0/rst0_r" BEL
        "main_00/top0/infrastructure0/delay_sel_val1_r_0" BEL
        "main_00/top0/infrastructure0/delay_sel_val1_r_1" BEL
        "main_00/top0/infrastructure0/delay_sel_val1_r_2" BEL
        "main_00/top0/infrastructure0/delay_sel_val1_r_3" BEL
        "main_00/top0/infrastructure0/delay_sel_val1_r_4" BEL
        "main_00/top0/infrastructure0/rst_calib1_r1" BEL
        "main_00/top0/infrastructure0/rst_calib1_r2" BEL
        "main_00/top0/controller0/rst180_r" BEL
        "main_00/top0/controller0/rst0_r" BEL
        "main_00/top0/controller0/rdburst_end_1" BEL
        "main_00/top0/controller0/AR_Done_reg" BEL
        "main_00/top0/controller0/BA_address_conflict" BEL
        "main_00/top0/controller0/config_reg_1" BEL
        "main_00/top0/controller0/config_reg_5" BEL
        "main_00/top0/controller0/write_cmd1" BEL
        "main_00/top0/controller0/read_cmd1" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_0" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_1" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_2" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_3" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_4" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_5" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_6" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_7" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_8" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_9" BEL
        "main_00/top0/controller0/AUTOREF_COUNT_10" BEL
        "main_00/top0/controller0/AUTO_REF_detect1" BEL
        "main_00/top0/controller0/Auto_Ref_issued" BEL
        "main_00/top0/controller0/rdburst_end_2" BEL
        "main_00/top0/controller0/DQS_reset_int" BEL
        "main_00/top0/controller0/init_memory" BEL
        "main_00/top0/controller0/CONFLICT" BEL
        "main_00/top0/controller0/GO_TO_ACTIVE" BEL
        "main_00/top0/controller0/rpCnt0" BEL
        "main_00/top0/controller0/rpCnt1" BEL
        "main_00/top0/controller0/mrdCnt0" BEL
        "main_00/top0/controller0/mrdCnt1" BEL
        "main_00/top0/controller0/rcdrCnt0" BEL
        "main_00/top0/controller0/rcdrCnt1" BEL
        "main_00/top0/controller0/rcdwCnt0" BEL
        "main_00/top0/controller0/rcdwCnt1" BEL
        "main_00/top0/controller0/RFC_COUNT_reg" BEL
        "main_00/top0/controller0/ddr_address_cntrl_0" BEL
        "main_00/top0/controller0/ddr_address_cntrl_1" BEL
        "main_00/top0/controller0/ddr_address_cntrl_2" BEL
        "main_00/top0/controller0/ddr_address_cntrl_3" BEL
        "main_00/top0/controller0/ddr_address_cntrl_4" BEL
        "main_00/top0/controller0/ddr_address_cntrl_5" BEL
        "main_00/top0/controller0/ddr_address_cntrl_6" BEL
        "main_00/top0/controller0/ddr_address_cntrl_7" BEL
        "main_00/top0/controller0/ddr_address_cntrl_8" BEL
        "main_00/top0/controller0/ddr_address_cntrl_10" BEL
        "main_00/top0/controller0/ddr_address_cntrl_12" BEL
        "main_00/top0/controller0/ddr_rasb2" BEL
        "main_00/top0/controller0/ddr_casb2" BEL
        "main_00/top0/controller0/ddr_web2" BEL
        "main_00/top0/controller0/dqs_div_rdburstcount_0" BEL
        "main_00/top0/controller0/dqs_div_rdburstcount_1" BEL
        "main_00/top0/controller0/rst_dqs_div_r" BEL
        "main_00/top0/controller0/row_address_reg_1" BEL
        "main_00/top0/controller0/column_address_reg_0" BEL
        "main_00/top0/controller0/column_address_reg_2" BEL
        "main_00/top0/controller0/column_address_reg_3" BEL
        "main_00/top0/controller0/column_address_reg_4" BEL
        "main_00/top0/controller0/column_address_reg_5" BEL
        "main_00/top0/controller0/column_address_reg_6" BEL
        "main_00/top0/controller0/column_address_reg_7" BEL
        "main_00/top0/controller0/burst_length_1" BEL
        "main_00/top0/controller0/cas_latency_1" BEL
        "main_00/top0/controller0/write_cmd2" BEL
        "main_00/top0/controller0/read_cmd2" BEL
        "main_00/top0/controller0/AUTO_REF_detect" BEL
        "main_00/top0/controller0/auto_ref_wait" BEL
        "main_00/top0/controller0/wrburst_end_3" BEL
        "main_00/top0/controller0/DQS_enable1" BEL
        "main_00/top0/controller0/DQS_reset1_clk0" BEL
        "main_00/top0/controller0/INIT_COUNT_0" BEL
        "main_00/top0/controller0/INIT_COUNT_1" BEL
        "main_00/top0/controller0/INIT_COUNT_2" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_0" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_1" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_2" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_4" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_5" BEL
        "main_00/top0/controller0/RP_COUNT_0" BEL
        "main_00/top0/controller0/RP_COUNT_1" BEL
        "main_00/top0/controller0/RP_COUNT_2" BEL
        "main_00/top0/controller0/RFC_COUNT_1" BEL
        "main_00/top0/controller0/RFC_COUNT_2" BEL
        "main_00/top0/controller0/RFC_COUNT_4" BEL
        "main_00/top0/controller0/CAS_COUNT_0" BEL
        "main_00/top0/controller0/CAS_COUNT_1" BEL
        "main_00/top0/controller0/RRD_COUNT_0" BEL
        "main_00/top0/controller0/RCDR_COUNT_0" BEL
        "main_00/top0/controller0/RCDR_COUNT_1" BEL
        "main_00/top0/controller0/RCDR_COUNT_2" BEL
        "main_00/top0/controller0/wrburst_end_cnt_0" BEL
        "main_00/top0/controller0/wrburst_end_cnt_1" BEL
        "main_00/top0/controller0/wrburst_end_cnt_2" BEL
        "main_00/top0/controller0/dqs_div_cascount_0" BEL
        "main_00/top0/controller0/dqs_div_cascount_1" BEL
        "main_00/top0/controller0/dqs_div_cascount_2" BEL
        "main_00/top0/controller0/write_cmd3" BEL
        "main_00/top0/controller0/read_cmd3" BEL
        "main_00/top0/controller0/AUTO_REF_pulse_end" BEL
        "main_00/top0/controller0/auto_ref_wait1" BEL
        "main_00/top0/controller0/DQS_enable2" BEL
        "main_00/top0/controller0/DQS_reset2_clk0" BEL
        "main_00/top0/controller0/ddr_ba_cntrl_0" BEL
        "main_00/top0/controller0/read_cmd4" BEL
        "main_00/top0/controller0/auto_ref_wait2" BEL
        "main_00/top0/controller0/read_cmd5" BEL
        "main_00/top0/controller0/auto_ref" BEL
        "main_00/top0/controller0/ACK_REG_INST1" BEL
        "main_00/top0/controller0/rst_calib0" BEL
        "main_00/top0/controller0/rst_iob_out" BEL
        "main_00/top0/controller0/next_state_0" BEL
        "main_00/top0/controller0/next_state_1" BEL
        "main_00/top0/controller0/next_state_2" BEL
        "main_00/top0/controller0/next_state_3" BEL
        "main_00/top0/controller0/next_state_4" BEL
        "main_00/top0/controller0/next_state_5" BEL
        "main_00/top0/controller0/next_state_6" BEL
        "main_00/top0/controller0/next_state_7" BEL
        "main_00/top0/controller0/next_state_9" BEL
        "main_00/top0/controller0/next_state_10" BEL
        "main_00/top0/controller0/next_state_11" BEL
        "main_00/top0/controller0/next_state_14" BEL
        "main_00/top0/controller0/next_state_12" BEL
        "main_00/top0/controller0/address_reg_2" BEL
        "main_00/top0/controller0/address_reg_0" BEL
        "main_00/top0/controller0/address_reg_5" BEL
        "main_00/top0/controller0/address_reg_3" BEL
        "main_00/top0/controller0/address_reg_4" BEL
        "main_00/top0/controller0/address_reg_6" BEL
        "main_00/top0/controller0/address_reg_7" BEL
        "main_00/top0/controller0/address_reg_12" BEL
        "main_00/top0/controller0/DQS_enable_int" BEL
        "main_00/top0/controller0/write_enable" BEL
        "main_00/top0/controller0/INIT_DONE" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_3" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_6" BEL
        "main_00/top0/controller0/DLL_RST_COUNT_7" BEL
        "main_00/top0/controller0/MRD_COUNT_0" BEL
        "main_00/top0/controller0/MRD_COUNT_1" BEL