"main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob3/DDR_OUT/FF1" PINNAME
        CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DDR_OUT/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DDR_OUT/FF0" PINNAME
        CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DDR_OUT/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DDR_OUT/FF1" PINNAME
        CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DDR_OUT/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DDR_OUT/FF0" PINNAME
        CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DDR_OUT/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DDR_OUT/FF1" PINNAME
        CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DDR_OUT/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DDR_OUT/FF0" PINNAME
        CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DDR_OUT/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DDR_OUT/FF1" PINNAME
        CK;
TIMEGRP infrastructure_top0_clk_dcm0_clk90dcm = BEL
        "infrastructure_top0/sys_rst90_o" BEL "infrastructure_top0/wait_clk90"
        BEL "infrastructure_top0/sys_rst90_1" BEL
        "infrastructure_top0/sys_rst90" PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM0_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM0_OUT/FF1_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM1_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM1_OUT/FF1_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM2_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM2_OUT/FF1_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM3_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/DDR_DM3_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob31/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob31/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob31/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob30/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob30/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob30/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob29/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob29/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob29/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob28/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob28/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob28/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob27/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob27/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob27/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob26/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob26/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob26/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob25/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob25/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob25/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob24/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob24/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob24/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob23/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob23/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob23/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob22/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob22/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob22/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob21/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob21/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob21/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob20/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob20/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob20/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob19/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob19/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob19/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob18/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob18/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob18/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob17/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob17/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob17/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob16/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob16/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob16/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob15/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob15/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob15/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob14/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob14/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob14/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob13/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob13/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob13/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob12/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob12/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob12/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob11/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob11/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob11/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob10/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob10/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob10/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob9/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob9/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob9/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob8/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob8/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob8/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob7/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob7/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob7/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob6/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob6/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob6/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob5/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob5/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob5/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob4/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob4/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob4/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob3/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob3/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob3/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DQ_T" PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DDR_OUT/FF0_pins<0>"
        PIN
        "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/DDR_OUT/FF1_pins<0>"
        BEL "main_00/top0/data_path0/data_read_controller0/read_valid_data_r"
        BEL "main_00/top0/data_path0/data_read_controller0/read_valid_data_r1"
        BEL "main_00/top0/data_path0/data_read_controller0/u_data_val_r" BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_d_0"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_d_1"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_d_2"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_d_3"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_d_0"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_d_1"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_d_2"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_d_3"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_2d_0"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_2d_1"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_2d_2"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_2d_3"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_3d_0"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_3d_1"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_3d_2"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_3d_3"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_2d_0"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_2d_1"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_2d_2"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_2d_3"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_3d_0"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_3d_1"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_3d_2"
        BEL
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_3d_3"
        BEL "main_00/top0/data_path0/data_read0/read_valid_data_1_r" BEL
        "main_00/top0/data_path0/data_read0/fifo01_rd_addr_r_0" BEL
        "main_00/top0/data_path0/data_read0/fifo01_rd_addr_r_1" BEL
        "main_00/top0/data_path0/data_read0/fifo01_rd_addr_r_2" BEL
        "main_00/top0/data_path0/data_read0/fifo01_rd_addr_r_3" BEL
        "main_00/top0/data_path0/data_read0/fifo00_rd_addr_r_0" BEL
        "main_00/top0/data_path0/data_read0/fifo00_rd_addr_r_1" BEL
        "main_00/top0/data_path0/data_read0/fifo00_rd_addr_r_2" BEL
        "main_00/top0/data_path0/data_read0/fifo00_rd_addr_r_3" BEL
        "main_00/top0/data_path0/data_read0/read_valid_data_1_r1" BEL
        "main_00/top0/data_path0/data_read0/fifo_01_data_out_r_0" BEL
        "main_00/top0/da