//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_controller_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: Main DDR SDRAM controller block. This includes the following
//                features:
//                - The controller state machine that controls the 
//                initialization process upon power up, as well as the 
//                read, write and refresh commands. 
//                - Accepts and decodes the user commands.
//                - Generates the address and Bank address signals
//                - Generates control signals for other modules, including
//                the control signals for the dqs_en block.
///////////////////////////////////////////////////////////////////////////////

`include "../rtl/ddr_cntl_a_parameters_0.v"


`timescale 1ns/100ps

module ddr_cntl_a_controller_0(
                clk,
		 rst0,
	         rst180,
	         address,
	         bank_address,
	         config_register,
	         command_register,
	         burst_done,
		 ddr_rasb_cntrl,
	         ddr_casb_cntrl,
	         ddr_web_cntrl,
	         ddr_ba_cntrl,
	         ddr_address_cntrl,
	         ddr_cke_cntrl,
	         ddr_csb_cntrl,
	         dqs_enable,
	         dqs_reset,
	         write_enable,
	         rst_calib,
	         rst_dqs_div_int,
	         cmd_ack,
	         init,
	         ar_done,
                 wait_200us,
                 auto_ref_req
                 );

 
   input          clk;  
   input          rst0;            
   input 	        rst180;          
   input[((`row_address + `col_ap_width)  -1):0] 	  address;         

   input[`bank_address-1:0] 	  bank_address;    
   input[9:0] 	  config_register; 
   input[2:0] 	  command_register;
   input          burst_done;
  
   output         ddr_rasb_cntrl;    
   output         ddr_casb_cntrl;    
   output         ddr_web_cntrl;    
   output[`bank_address-1:0]    ddr_ba_cntrl;     
   output[`row_address-1:0]   ddr_address_cntrl;
   output         ddr_cke_cntrl; 
   output         ddr_csb_cntrl;     
   output         dqs_enable;  
   output         dqs_reset;  
   output         write_enable;
   output         rst_calib;   
   output         rst_dqs_div_int;
   output         cmd_ack;
   output         init;  
   output         ar_done;

   input          wait_200us ;
   output         auto_ref_req; 
   
   reg  [`row_address-1:0]ddr_address_cntrl;
   reg  [`bank_address-1:0]ddr_ba_cntrl;   
   
parameter [3:0] IDLE = 0,
                PRECHARGE = 1,
                LOAD_MODE_REG = 2,
                AUTO_REFRESH =3,
                ACTIVE = 4,
                FIRST_WRITE =5,
                WRITE_WAIT = 6,
                BURST_WRITE = 7,
                READ_AFTER_WRITE = 8,
                PRECHARGE_AFTER_WRITE = 9,
                PRECHARGE_AFTER_WRITE_2 = 10,
                READ_WAIT =11,
                BURST_READ = 12,
                BURST_STOP = 13,//D
                ACTIVE_WAIT = 14;//E

reg          ar_done;
reg          write_enable;

reg [3:0]    next_state;
reg [3:0]    next_state1;

wire         ack_reg;
wire         ack_o;
  reg [((`row_address + `col_ap_width)  -1):0]   address_reg;

wire [`row_address-1:0]  address_config;
reg          auto_ref;
wire         auto_ref1;
wire         AUTOREF_value;
reg          AUTO_REF_detect;
reg          AUTO_REF_detect1;
reg          AUTO_REF_pulse_end;
reg [10:0]   AUTOREF_COUNT;
wire [10:0]  AUTOREF_CNT_val;
reg          Auto_Ref_issued;
wire         Auto_Ref_issued_p;
reg [5:0]   RFC_COUNTER_value;

wire         AR_done_p;
reg [`bank_address-1:0]    BA_address_active;
reg          BA_address_conflict;
reg [`bank_address-1:0]    BA_address_reg;
reg [2:0]    burst_length;
wire [2:0]   burst_cnt_max;
reg [2:0]    CAS_COUNT;  //Modifiedd by Abhishake for BL=8
wire [2:0]   cas_count_value; //Modifiedd by Abhishake for BL=8

reg [2:0]    cas_latency;
reg [`row_address -1:0]    column_address_reg;
reg [`row_address -1:0]    column_address_reg1;
reg [`row_address -1:0]    column_address_reg2;
reg [`row_address -1:0]    column_address_reg3;
reg [`row_address -1:0]    column_address_reg4;
reg [`row_address -1:0]    column_address_reg5;
reg [`row_address -1:0]    column_address_reg6;
wire[`row_address -1:0]    column_address;

reg [2:0]    command_reg;
reg [9:0]    config_reg;
reg          CONFLICT;
wire         CONFLICT_value;
wire         ddr_rasb1;
wire         ddr_casb1;
wire         ddr_web1;
reg          ddr_rasb2;
reg          ddr_casb2;
reg          ddr_web2;
reg          ddr_rasb3;
reg          ddr_casb3;
reg          ddr_web3;
reg          ddr_rasb4;
reg          ddr_casb4;
reg          ddr_web4;
reg          ddr_rst_dqs_rasb4;
reg          ddr_rst_dqs_casb4;
reg          ddr_rst_dqs_web4;
reg          ddr_rasb5;
reg          ddr_casb5;
reg          ddr_web5;
wire[`bank_address-1:0]  ddr_ba1;
reg [`bank_address-1:0]  ddr_ba2;
reg [`bank_address-1:0]  ddr_ba3;
reg [`bank_address-1:0]  ddr_ba4;
reg [`bank_address-1:0]  ddr_ba5;
wire [`row_address-1:0]  ddr_address1;
reg [`row_address-1:0]   ddr_address2;
reg [`row_address-1:0]   ddr_address3;
reg [`row_address-1:0]   ddr_address4;
reg [`row_address-1:0]   ddr_address5;
wire         DQS_enable_out;
wire         DQS_reset_out;
wire [2:0]   INIT_COUNT_value;
reg [2:0]    INIT_COUNT;
wire [7:0]   DLL_RST_COUNT_value;
reg [7:0]    DLL_RST_COUNT;
reg          INIT_DONE;
wire         init_done_value;
reg          init_memory;
wire         init_mem;
wire          initialize_memory;
wire          ld_mode;
wire [1:0]   MRD_COUNT_value;
reg [10:0]  max_ref_cnt;
reg [1:0]     MRD_COUNT;
wire          PRECHARGE_CMD;
wire [3:0]   ras_count_value;
reg [3:0]    RAS_COUNT;
wire         rdburst_chk;
wire          read_cmd;
reg          read_cmd1;
reg          read_cmd2;
reg          read_cmd3;
reg          read_cmd4;
reg          read_cmd5;
reg          read_cmd6;
reg          read_cmd7;
reg          read_cmd8;
reg          read_rcd_end;
reg          read_cmd_reg;
wire         read_write_state;
reg [1:0]    RRD_COUNT;
reg [2:0]    RCDR_COUNT;
reg [1:0]    RCDW_COUNT;
wire [2:0]   rp_cnt_value;
wire [4:0]   RFC_COUNT_value;
reg          RFC_COUNT_reg;  
reg          AR_Done_reg;  
wire [1:0]   RRD_COUNT_value;
wire [2:0]   RCDR_COUNT_value;
wire [1:0]   RCDW_COUNT_value;
wire [3:0]   RC_COUNT_value;
wire [2:0]   rdburst_end_cnt_value;
reg [2:0]    RDBURST_END_CNT;
reg          rdburst_end_1;
reg          rdburst_end_2;
reg          rdburst_end_3;
reg          rdburst_end_4;
reg          rdburst_end_5;
reg          rdburst_end_6;
reg          rdburst_end_7;
reg          rdburst_end_8;
wire         rdburst_end_r;
wire         read_enable_out_r;
wire         rdburst_end;
reg [2:0]    RP_COUNT;
reg [3:0]    RC_COUNT;
reg [4:0]    RFC_COUNT;
wire         read_enable_out;
wire [`row_address-1:0]   ROW_ADDRESS;
reg  [`row_address-1:0]   row_address_reg;
reg  [`row_address-1:0]   row_address_active_reg;
reg          row_address_conflict;
reg          rst_dqs_div_r;


wire		 rst_dqs_div_r1;
reg          dly_dqs_div_r;  //Added to delay the rst_dqs_div_r by 1 clock pulse for BL = 2 .

wire [2:0]   wrburst_end_cnt_value;
reg  [2:0]   wrburst_end_cnt;
wire         wrburst_end;
reg          wrburst_end_1;
reg          wrburst_end_2;
reg          wrburst_end_3;
reg          wrburst_end_4;
reg          wrburst_end_5;
reg          wrburst_end_6;
reg          wrburst_end_7;
reg          wrburst_end_8;
reg          wrburst_end_9;
wire         wrburst_chk;
reg  [1:0]    WR_COUNT;
wire [1:0]   WR_COUNT_value;
wire         write_enable_out;

reg          write_cmd;
wire          write_cmd_in;
reg          write_cmd2;
reg          write_cmd3;
reg          write_cmd4;
reg          write_cmd5;
reg          write_cmd1;
reg          write_cmd6;
reg          write_cmd7;
reg          write_cmd8;
wire         GND;
reg [2:0]    dqs_div_cascount;
reg [2:0]    dqs_div_rdburstcount;
wire         rst_dqs_div_int;
reg          DQS_enable1;
reg          DQS_enable2;
reg          DQS_enable3;
reg          DQS_enable4;
reg          DQS_reset1_clk0;
reg          DQS_reset2_clk0;
reg          DQS_reset3_clk0;
reg          DQS_reset4_clk0;
reg          DQS_enable_int;
reg          DQS_reset_int;
reg          rst180_r;
reg          rst0_r;
wire         GO_TO_ACTIVE_value;
reg          GO_TO_ACTIVE;


 reg      rpCnt0;
 reg      rpCnt1;

 reg     mrdCnt0;          
 reg     mrdCnt1;          
 
 reg     rcdrCnt0;       
 reg     rcdrCnt1;        
 
 reg     rcdwCnt0;      
 reg     rcdwCnt1;  

 reg     rcCnt0;     

wire  accept_cmd_in;

reg ldMdReg_flag ;
reg precharge_flag;
reg aref_flag;
reg idle_flag;

 reg  auto_ref_wait;
 reg  auto_ref_wait1;
 reg  auto_ref_wait2;

//  Input : CONFIG REGISTER FORMAT 
// config_register = {   EMR(Enable/Disable DLL),
//                       BMR (Normal operation/Normal Operation with Reset DLL),
//                       BMR/EMR,
//                       CAS_latency (3),
//                       Burst type ,
//                       Burst_length (3) }
//
// Input : COMMAND REGISTER FORMAT
//          000  - NOP
//          001  - Precharge 
//          010  - Auto Refresh
//          011  - SElf REfresh
//          100  - Write Request
//          101  - Load Mode Register
//          110  - Read request
//          111  - Burst terminate
//
// Input : Address format
//   row address = input address(19 downto 8)
//   column addrs = input address( 7 downto 0)


assign ddr_csb_cntrl = 1'b0; // dip3;
assign ddr_cke_cntrl = ~wait_200us;

 


  assign ROW_ADDRESS = address_reg[((`row_address + `col_ap_width  )-1):`col_ap_width]; 

  assign column_address = address_reg[`row_address  -1:0];
assign init = INIT_DONE;
assign GND = 1'b0;


assign ddr_rasb_cntrl = ddr_rasb2;
assign ddr_casb_cntrl = ddr_casb2;
assign ddr_web_cntrl = ddr_web2;

assign auto_ref_req = auto_ref_wait;

always @ (negedge clk)
begin
  rst180_r <= rst180;
end

always @ (posedge clk)
begin
  rst0_r <= rst0;
end

//********************************************************************************************
// register input commands from the user
// 
//********************************************************************************************

  always @ (negedge clk)       //(posedge clk180)
  begin
    if (rst180_r == 1'b1)
      begin
        config_reg <= 10'b0000000000;
        command_reg <= 3'b000;
        row_address_reg <= `row_address'b0;
          column_address_reg <= `row_address'b0;
        BA_address_reg <= `bank_address'b0;
          address_reg <= `row_address + `col_ap_width'b0;

      end
    else
      begin
        config_reg <= config_register;
        command_reg <= command_register;
        row_address_reg <= ROW_ADDRESS;
        column_address_reg <= column_address;
        BA_address_reg <= bank_address;
        address_reg <= address;
      end
  end
  
always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    begin
     burst_length <= 3'b000;
     cas_latency  <= 3'b000;
    end
  else
    begin
     burst_length <= config_reg[2:0];    
     cas_latency  <= config_reg[6:4];
    end
end

assign accept_cmd_in = ((next_state == IDLE ) && rpCnt0 && RFC_COUNT_reg  && !auto_ref_wait);