//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_infrastructure_top.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: This module has instantiations clk_dcm and cal_top. It generates reset signals.///////////////////////////////////////////////////////////////////////////////  `timescale 1ns/100psmodule ddr_cntl_a_infrastructure_top     (                SYS_CLK,		SYS_CLKb,		reset_in,        		delay_sel_val1_val_tb,  		delay_sel_val1_val_rl,  		sys_rst_val,          		sys_rst90_val,        		clk_int_val,          		clk90_int_val,		sys_rst180_val,       		sys_rst270_val,		wait_200us    );// Input/Output declarations  input		SYS_CLK;input		SYS_CLKb;input         reset_in;         output [4:0] delay_sel_val1_val_tb;  output [4:0] delay_sel_val1_val_rl;  output       sys_rst_val;          output       sys_rst90_val;        output       sys_rst180_val;       output       sys_rst270_val;output       wait_200us;       output       clk_int_val;          output       clk90_int_val;        wire user_rst;  wire clk_int;   wire clk90_int;  wire dcm_lock; wire sys_clk_ibuf;reg sys_rst_o;              reg sys_rst_1;              reg sys_rst;                reg sys_rst90_o;            reg sys_rst90_1;            reg sys_rst90;              reg sys_rst180_o;           reg sys_rst180_1;           reg sys_rst180;             reg sys_rst270_o;          reg sys_rst270_1;          reg sys_rst270;            wire vcc;wire clk_int_val1;wire clk_int_val2;wire clk90_int_val1;wire clk90_int_val2;wire [4:0] delay_sel_val_tb;wire [4:0] delay_sel_val_rl;//200us regreg [15:0] Counter200;reg      wait_200us;//addedreg      wait_clk90;//addedIBUFGDS_LVDS_25  lvds_clk_input(                                 .I(SYS_CLK),                                 .IB(SYS_CLKb),                                 .O(sys_clk_ibuf)                               );assign clk_int_val = clk_int;assign clk90_int_val = clk90_int;assign sys_rst_val = sys_rst;assign sys_rst90_val = sys_rst90;assign sys_rst180_val = sys_rst180;assign sys_rst270_val = sys_rst270;assign delay_sel_val1_val_tb = delay_sel_val_tb;assign delay_sel_val1_val_rl = delay_sel_val_rl;//-----   To remove delta delays in the clock signals observed during simulation ,Following signals are used assign clk_int_val1 = clk_int;assign clk90_int_val1 = clk90_int;assign clk_int_val2 = clk_int_val1;assign clk90_int_val2 = clk90_int_val1;assign vcc       = 1'b1;assign user_rst  = ~ reset_in;                                        //For 200us during power upalways @(posedge clk_int_val2)begin   if(user_rst == 1'b1 || dcm_lock == 1'b0)   begin     wait_200us <= 1'b1;     Counter200     <= 16'b0;   end    else   begin      if (wait_200us)         Counter200 <= Counter200 + 1;    else             Counter200 <= Counter200;   `ifdef simulation    		wait_200us <=  1'b0;   `else        if( Counter200[15] & Counter200[13] & wait_200us)//(THIS IS DIFFERENT IN DDR2)         	wait_200us <=1'b0;   `endif   end endalways @(posedge clk90_int_val2)begin   if(user_rst == 1'b1 || dcm_lock == 1'b0)      wait_clk90 <= 1'b1;   else      wait_clk90 <= wait_200us;endalways@(posedge clk_int_val2)begin    if(user_rst == 1'b1 || dcm_lock == 1'b0 || wait_200us == 1'b1 )      begin      sys_rst_o <= 1'b1;      sys_rst_1 <= 1'b1;      sys_rst   <= 1'b1;      end     else      begin      sys_rst_o <= 1'b0;      sys_rst_1 <= sys_rst_o;      sys_rst   <= sys_rst_1;      endend      always@(posedge clk90_int_val2)begin  if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_clk90 == 1'b1)      begin      sys_rst90_o <= 1'b1;      sys_rst90_1 <= 1'b1;      sys_rst90   <= 1'b1;      end  else      begin      sys_rst90_o <= 1'b0;      sys_rst90_1 <= sys_rst90_o;      sys_rst90   <= sys_rst90_1;      endendalways@(negedge clk_int_val2)begin  if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_200us == 1'b1)      begin       sys_rst180_o <= 1'b1;      sys_rst180_1 <= 1'b1;      sys_rst180   <= 1'b1;      end  else      begin      sys_rst180_o <= 1'b0;      sys_rst180_1 <= sys_rst180_o;      sys_rst180   <= sys_rst180_1;      endend      always@(negedge clk90_int_val2)begin  if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_clk90 == 1'b1)      begin      sys_rst270_o <= 1'b1;      sys_rst270_1 <= 1'b1;      sys_rst270   <= 1'b1;      end  else      begin      sys_rst270_o <= 1'b0;      sys_rst270_1 <= sys_rst270_o;      sys_rst270   <= sys_rst270_1;      endend ///----  Component instantiations  ----                                      ddr_cntl_a_clk_dcm clk_dcm0  (                               .input_clk   ( sys_clk_ibuf),                               .rst         ( user_rst),                                                           .clk         ( clk_int),                               .clk90       ( clk90_int),                               .dcm_lock    ( dcm_lock)                              );                              ddr_cntl_a_cal_top cal_top0 (                                                                                                           .clk0        ( clk_int_val2),                                       .clk0dcmlock ( dcm_lock),                               .reset       ( reset_in),                                //   .okToSelTap  ( vcc),                          //   .tapForDqs   ( delay_sel_val)                             .tapForDqs_tb   ( delay_sel_val_tb),                             .tapForDqs_rl   ( delay_sel_val_rl)                             );                                                 endmodule