//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_clk_dcm.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: This module contains the DCM instantiation for DDR SDRAM controller///////////////////////////////////////////////////////////////////////////////////`timescale 1ns/100psmodule ddr_cntl_a_clk_dcm (input_clk,        rst,        clk,        clk90,        dcm_lock);   input input_clk;   input rst;   output clk;   output clk90;   output dcm_lock;       // synthesis translate_off       defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";       defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";       // synthesis translate_on   wire clk0dcm;   wire clk90dcm;   wire clk0_buf;   wire clk90_buf;   wire dcm1_lock;     parameter GND = 1'b0;   assign clk = clk0_buf;   assign clk90 = clk90_buf;   DCM DCM_INST1                    (         .CLKIN    (input_clk),                            .CLKFB    (clk0_buf),                            .DSSEN    (GND),                            .PSINCDEC (GND),                            .PSEN     (GND),                            .PSCLK    (GND),                            .RST      (rst),                            .CLK0     (clk0dcm),                            .CLK90    (clk90dcm),                            .CLK180   (),                            .CLK270   (),		            .CLK2X    (),                            .CLK2X180 (),                            .CLKDV    (),                            .CLKFX    (),                            .CLKFX180 (),                            .LOCKED   (dcm1_lock),                            .PSDONE   (),                            .STATUS    ()                    )                    /* synthesis  DUTY_CYCLE_CORRECTION  = "TRUE",                       DLL_FREQUENCY_MODE  = "LOW" */ ;   ddr_cntl_a_mybufg_0 BUFG_CLK0 (.I(clk0dcm), .O(clk0_buf));   ddr_cntl_a_mybufg_0 BUFG_CLK90 (.I(clk90dcm), .O(clk90_buf));   assign dcm_lock = dcm1_lock;endmodule