?? ddr_cntl_a_infrastructure.v
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///////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved.///////////////////////////////////////////////////////////////////////////////// ____ ____// / /\/ /// /___/ \ / Vendor: Xilinx// \ \ \/ Version: 1.6// \ \ Application : MIG// / / Filename: ddr_cntl_a_infrastructure.v// /___/ /\ Date Last Modified: Tue Jul 11 2006// \ \ / \ Date Created: Mon May 2 2005// \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: /////////////////////////////////////////////////////////////////////////////// `timescale 1ns/100psmodule ddr_cntl_a_infrastructure ( sys_rst, clk_int, rst_calib1, delay_sel_val, delay_sel_val1_val); input sys_rst;input clk_int;input rst_calib1; input [4:0] delay_sel_val; output [4:0]delay_sel_val1_val; wire clk_int; wire [4:0]delay_sel_val; wire [4:0]delay_sel_val1; reg [4:0]delay_sel_val1_r; reg rst_calib1_r1;reg rst_calib1_r2;assign delay_sel_val1_val = delay_sel_val1;assign delay_sel_val1 = (rst_calib1 == 1'b0 && rst_calib1_r2 == 1'b0) ? delay_sel_val :delay_sel_val1_r;always@(posedge clk_int)begin if (sys_rst == 1'b1) begin delay_sel_val1_r <= 5'b00000; rst_calib1_r1 <= 1'b0; rst_calib1_r2 <= 1'b0; end else begin delay_sel_val1_r <= delay_sel_val1; rst_calib1_r1 <= rst_calib1; rst_calib1_r2 <= rst_calib1_r1; endendendmodule
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