//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_main_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This modules contains the instantiations for top and test_bench modules. 
///////////////////////////////////////////////////////////////////////////////

`include "ddr_cntl_a_parameters_0.v"
  `timescale 1ns/100ps
module    ddr_cntl_a_main_0( 
		clk_int,
		clk90_int,
		delay_sel_val,
		sys_rst_val,
		sys_rst90_val,
		sys_rst180_val,
		sys_rst270_val,
		rst_dqs_div_in,
		rst_dqs_div_out, 
		DDR_CAS_N,  
	DDR_DM,
	      
		DDR_CKE,  
		DDR_CK,
		DDR_CK_N,
		DDR_CS_N,         
		DDR_RAS_N,        
		DDR_WE_N,         
		DDR_A,     
		DDR_BA,          
	
		led_error_output1,
		DDR_DQ,          
		wait_200us, 
		DDR_DQS         
		  );
  
input       clk_int;
input       clk90_int;
input    [4:0] delay_sel_val;
input       sys_rst_val;
input       sys_rst90_val;
input       sys_rst180_val;
input       sys_rst270_val;
input	       rst_dqs_div_in;
output	 rst_dqs_div_out;
output       DDR_CAS_N;
output       DDR_CKE;   

output   [(`clk_width-1):0]  DDR_CK;
output   [(`clk_width-1):0]  DDR_CK_N;

output       DDR_CS_N;         
output       DDR_RAS_N;        
output       DDR_WE_N;     
output       [`row_address-1:0]DDR_A;   
output       [`bank_address-1:0]DDR_BA;     
output       [((`data_mask_width)-1):0]  DDR_DM;         

output       led_error_output1; 
inout        [(`data_width-1):0]DDR_DQ;       
 input    wait_200us; 
inout        [(`data_strobe_width-1):0]DDR_DQS;

//---- wire declarations used on the diagram ----

wire [((`data_width*2)-1):0]user_output_data; 
wire [((`row_address + `col_ap_width + `bank_address)-1):0] u1_address; 
wire user_data_val1;       
wire [9:0]u1_config_parms; 
wire [2:0]user_cmd1;       
wire auto_ref_req; 
wire user_ack1;            
wire [((`data_width*2)-1):0]u1_data_i;
wire [((`data_mask_width*2)-1):0] u1_data_m;     
wire burst_done_val1;      
wire init_val1;            
wire ar_done_val1;         
wire clk_int;              
wire clk90_int;            
wire data_valid_out1;
ddr_cntl_a_top_0	top0	( 
				.auto_ref_req      (auto_ref_req), 
				.wait_200us(wait_200us), 
				.rst_dqs_div_in	        (rst_dqs_div_in),
				.rst_dqs_div_out	       (rst_dqs_div_out),
				.user_input_data        (u1_data_i),
				.user_output_data       (user_output_data),
				.user_data_valid        (user_data_val1),
				.user_input_address     (u1_address[((`row_address + `col_ap_width   + `bank_address)-1):0]),
				.user_config_register   (u1_config_parms),
				.user_command_register  (user_cmd1),
				.user_cmd_ack           (user_ack1),
				.burst_done             (burst_done_val1),
				.init_val               (init_val1),
				.ar_done                (ar_done_val1),
				.DDR_DQS                (DDR_DQS),
				.DDR_DQ                 (DDR_DQ),
				.DDR_CKE                (DDR_CKE),
				.DDR_CS_N               (DDR_CS_N),
				.DDR_RAS_N              (DDR_RAS_N),
				.DDR_CAS_N              (DDR_CAS_N),
				.DDR_WE_N               (DDR_WE_N),
	     		        			.DDR_DM                 (DDR_DM),
//				.user_data_mask         (u1_data_m),	
							.user_data_mask         (u1_data_m),	          

				.DDR_BA                 (DDR_BA),
				.DDR_A 		      (DDR_A),

				.DDR_CK		(DDR_CK),
				.DDR_CK_N		(DDR_CK_N),
				 
				.clk_int(clk_int),
				.clk90_int(clk90_int),
				.delay_sel_val(delay_sel_val),
				.sys_rst_val(sys_rst_val),
				.sys_rst90_val(sys_rst90_val),
				.sys_rst180_val(sys_rst180_val),
				.sys_rst270_val(sys_rst270_val)
				);                                            

ddr_cntl_a_ddr1_test_bench_0    ddr1_test_bench0   ( 
				.auto_ref_req      (auto_ref_req),  
				.fpga_clk              ( clk_int),
				.fpga_rst90	(sys_rst90_val), 
				.fpga_rst0	(sys_rst_val), 
				.fpga_rst180	(sys_rst180_val), 
				.clk90                 ( clk90_int),
				.burst_done            ( burst_done_val1),
				.INIT_DONE             ( init_val1),
				.ar_done               ( ar_done_val1),
				.u_ack                 ( user_ack1),
				.u_data_val            ( user_data_val1),
				.u_data_o              ( user_output_data),
				.u_addr                ( u1_address),
				.u_cmd                 ( user_cmd1), 
				.u_data_i              ( u1_data_i ),
				.u_config_parms        ( u1_config_parms),
				.u_data_m              ( u1_data_m ),	
				.led_error_output      ( led_error_output1),
				.data_valid_out        ( data_valid_out1)
				);

 

    
                                   
endmodule