?? adr_cntrl_timingsheet_0.xls
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Uncertainity parameter Value Uncertainity before DQS Uncertainity after DQS MeaningTclock 7518.80 clock periodMemory address and control input setup time 900 900 0 Memory address and control input hold time 900 0 900 Tpackage_skew 90 45 45 Package skewClock jitter 0 0 0 Same DCM is used to generate DQ and DQSClock_tree_skew 25 25 25 Small value considered for skew on global clock line since detection of DQS and associated DQ are placed close to each otherTclock_out_phase 140 140 140 Phase offset error between different clock outputs of the same DCMPcb_layout_skew 400 400 400 Skew between data lines and asociated strobe on the boardData valid window - min/max 5063.80 1510.00 1510.00 Valid data windowMargin 4498.80
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