###### maxdelay of 460 ps will not be met. This constraint is just to get a better delay####
 ###### The reported delay will be in the range of 500 to 600 ps####
 NET "main_00/top0/dqs_int_delay_in*" 	MAXDELAY = 460ps;
 ###### maxdelay of 160 ps will not be met. This constraint is just to get a better delay####
 ###### The reported delay will be in the range of 200 to 360 ps####
 NET "main_00/top0/data_path0/data_read_controller0/dqs_delay*_col*/delay*" 	MAXDELAY = 160ps;
 ###################################################################################################
 ######constraint to place flop1 and flop2 close togather for the calibration logic  ###############
 ###################################################################################################

 NET "infrastructure_top0/cal_top0/tap_dly0/flop1[*]" MAXDELAY = 3000ps;



#######################################################################################################################
# Area Group Constraint For tap_dly and cal_ctl module #
#######################################################################################################################

#********************************************************************#
#                        CONTROLLER 0                               #
#********************************************************************#
############################################################################
# I/O STANDARDS                                                         #
############################################################################
NET  "cntrl0_DDR_DQ[*]"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_A[*]"                                      IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_BA[*]"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_DM[*]"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_DQS[*]"                                    IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_CK[*]"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_CK_N[*]"                                   IOSTANDARD = SSTL2_II;




############################################################################
# IO Signals Registering Constraints                                           #
############################################################################
INST "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob*"  IOB = TRUE;
INST "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob*"  IOB = TRUE;
INST "main_00/top0/controller0/rst_iob_out"            IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_addr*" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_ba*" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_rasb"      IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_casb"      IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_web"     IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_cke"     IOB = TRUE;

############################################################################
# Banks 03
# Pin Location Constraints for System clock signals
 ############################################################################
#NET  "SYS_CLK"	LOC = "A15";
############################################################################
# Banks 7
# Pin Location Constraints for Clock,Masks, Address, and Controls 
 ############################################################################
#########################################################################
# MAXDELAY constraints                                                                        #
#########################################################################
    NET  "main_00/top0/data_path0/data_read_controller0/rst_dqs_div"        MAXDELAY = 3000ps;
NET  "main_00/top0/iobs0/controller_iobs0/rst_dqs_div*"         MAXDELAY = 3000ps;
NET  "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed*"         MAXDELAY = 3000ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_wr_en"              MAXDELAY = 2000ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_wr_addr[*]"               MAXDELAY = 3000ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_rd_addr*"               MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_rd_addr_r*"               MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_data_out[*]"                    MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/user_output_data[*]"                       MAXDELAY = 4200ps;
NET  "main_00/top0/write_en_val*"                            MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/dqs_int_delay_in*"  MAXDELAY = 700ps;
#########################################################################
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 0, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit0" LOC = SLICE_X0Y96;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit0" LOC = SLICE_X0Y97;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 1, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit1" LOC = SLICE_X2Y98;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit1" LOC = SLICE_X2Y99;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 2, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit2" LOC = SLICE_X0Y98;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit2" LOC = SLICE_X0Y99;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 3, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit3" LOC = SLICE_X2Y100;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit3" LOC = SLICE_X2Y101;
#############################################################
##  constraints for bit cntrl0_DDR_DQS, 0, location in tile: 1
## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X2Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X2Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X2Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X2Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X3Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X3Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X0Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X0Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X0Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X0Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X1Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X1Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;

########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = SLICE_X1Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = SLICE_X1Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = SLICE_X1Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = SLICE_X1Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = SLICE_X3Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = SLICE_X3Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = SLICE_X3Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = SLICE_X3Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_en_inst" LOC = SLICE_X1Y101;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_en_inst" LOC = SLICE_X3Y101;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 5, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit5" LOC = SLICE_X2Y108;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit5" LOC = SLICE_X2Y109;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 4, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit4" LOC = SLICE_X0Y108;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit4" LOC = SLICE_X0Y109;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 7, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit7" LOC = SLICE_X2Y110;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit7" LOC = SLICE_X2Y111;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 6, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit6" LOC = SLICE_X0Y110;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit6" LOC = SLICE_X0Y111;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 9, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit1" LOC = SLICE_X2Y112;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit1" LOC = SLICE_X2Y113;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 8, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit0" LOC = SLICE_X0Y112;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit0" LOC = SLICE_X0Y113;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 11, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit3" LOC = SLICE_X2Y114;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit3" LOC = SLICE_X2Y115;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 10, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit2" LOC = SLICE_X0Y114;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit2" LOC = SLICE_X0Y115;
#############################################################
##  constraints for bit cntrl0_DDR_DQS, 1, location in tile: 0
## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X2Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X2Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X2Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X2Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X3Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X3Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X0Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X0Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X0Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X0Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X1Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X1Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = G;

########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = SLICE_X1Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = SLICE_X1Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = SLICE_X1Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = SLICE_X1Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = SLICE_X3Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = SLICE_X3Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = SLICE_X3Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = SLICE_X3Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_en_inst" LOC = SLICE_X1Y115;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_en_inst" LOC = SLICE_X3Y115;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 13, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit5" LOC = SLICE_X2Y120;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit5" LOC = SLICE_X2Y121;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 12, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit4" LOC = SLICE_X0Y120;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit4" LOC = SLICE_X0Y121;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 15, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit7" LOC = SLICE_X2Y122;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit7" LOC = SLICE_X2Y123;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 14, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit6" LOC = SLICE_X0Y122;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit6" LOC = SLICE_X0Y123;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 17, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit1" LOC = SLICE_X2Y126;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit1" LOC = SLICE_X2Y127;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 16, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit0" LOC = SLICE_X0Y126;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit0" LOC = SLICE_X0Y127;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 19, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit3" LOC = SLICE_X2Y128;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit3" LOC = SLICE_X2Y129;
#############################################################