?? ddr_cntl_a_rd_gray_cntr.v
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//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved.///////////////////////////////////////////////////////////////////////////////// ____ ____// / /\/ /// /___/ \ / Vendor: Xilinx// \ \ \/ Version: 1.6// \ \ Application : MIG// / / Filename: ddr_cntl_a_rd_gray_cntr.v// /___/ /\ Date Last Modified: Tue Jul 11 2006// \ \ / \ Date Created: Mon May 2 2005// \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: ///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100psmodule ddr_cntl_a_rd_gray_cntr( clk, reset, cnt_en, rgc_gcnt ); input clk; input reset; input cnt_en; output [3:0] rgc_gcnt; wire [3:0]gc_int ;reg [3:0]d_in ; assign rgc_gcnt = gc_int;always@(gc_int)begincase (gc_int)4'b0000: d_in <= 4'b0001; //14'b0001: d_in <= 4'b0011; //34'b0010: d_in <= 4'b0110; //64'b0011: d_in <= 4'b0010; //24'b0100: d_in <= 4'b1100; //c4'b0101: d_in <= 4'b0100; //44'b0110: d_in <= 4'b0111; //74'b0111: d_in <= 4'b0101; //54'b1000: d_in <= 4'b0000; //04'b1001: d_in <= 4'b1000; //84'b1010: d_in <= 4'b1011; //b4'b1011: d_in <= 4'b1001; //94'b1100: d_in <= 4'b1101; //d4'b1101: d_in <= 4'b1111; //f4'b1110: d_in <= 4'b1010; //a4'b1111: d_in <= 4'b1110; //edefault : d_in <= 4'b0001; //1endcaseend FDRE bit0 ( .Q( gc_int[0]), .C(clk), .CE(cnt_en), .D(d_in[0]), .R(reset) );FDRE bit1 ( .Q( gc_int[1]), .C(clk), .CE(cnt_en), .D(d_in[1]), .R(reset) );FDRE bit2 ( .Q( gc_int[2]), .C(clk), .CE(cnt_en), .D(d_in[2]), .R(reset) );FDRE bit3 ( .Q( gc_int[3]), .C(clk), .CE(cnt_en), .D(d_in[3]), .R(reset) );endmodule
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