//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_RAM8D_0.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: This module contains RAM16X1D instantiations ///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100ps`include "ddr_cntl_a_parameters_0.v"module ddr_cntl_a_RAM8D_0(		DOUT,		WADDR,		DIN,		RADDR,		WCLK0,		WCLK1,		WE	   );output [(`DatabitsPerReadClock -1):0] DOUT;input [3:0] WADDR;input [(`DatabitsPerReadClock -1):0] DIN;input [3:0] RADDR;input WCLK0; input WCLK1; input WE;  RAM16X1D fifo_bit0  (.DPO (DOUT[0]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[0]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK1), .WE(WE));   RAM16X1D fifo_bit1  (.DPO (DOUT[1]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[1]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK0), .WE(WE));   RAM16X1D fifo_bit2  (.DPO (DOUT[2]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[2]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK1), .WE(WE));   RAM16X1D fifo_bit3  (.DPO (DOUT[3]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[3]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK0), .WE(WE));   RAM16X1D fifo_bit4  (.DPO (DOUT[4]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[4]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK1), .WE(WE));   RAM16X1D fifo_bit5  (.DPO (DOUT[5]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[5]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK0), .WE(WE));   RAM16X1D fifo_bit6  (.DPO (DOUT[6]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[6]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK1), .WE(WE));   RAM16X1D fifo_bit7  (.DPO (DOUT[7]), .A0(WADDR[0]), .A1(WADDR[1]),    										.A2(WADDR[2]), .A3(WADDR[3]), .D(DIN[7]),											.DPRA0(RADDR[0]), .DPRA1(RADDR[1]),.DPRA2(RADDR[2]), .DPRA3(RADDR[3]), .SPO(),											.WCLK(WCLK0), .WE(WE));endmodule