//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_fifo_1_wr_en_0.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: It generates the write enable signal for the fifos///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100psmodule ddr_cntl_a_fifo_1_wr_en_0 ( clk,                      rst_dqs_delay_n,                      reset,                      din,                      dout);   input clk;   input rst_dqs_delay_n;   input reset;   input din;   output dout;   wire din_delay;   wire din_delay_1;   wire dout0;   wire rst_dqs_delay;   parameter TIE_HIGH = 1'b1;   assign rst_dqs_delay = ~rst_dqs_delay_n;   assign dout0 = din & rst_dqs_delay_n;   assign dout = rst_dqs_delay | din_delay_1;   FDCE delay_ff_1 (.Q(din_delay_1), .C(clk), .CE(TIE_HIGH), .CLR(reset), .D(dout0));endmodule