//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_data_path_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module comprises the write and read data paths for the
//                  DDR1 memory interface. The write data along with write enable 
//                  signals are forwarded to the DDR IOB FFs. The read data is 
//                  captured in CLB FFs and finally input to FIFOs.
///////////////////////////////////////////////////////////////////////////////

`include "ddr_cntl_a_parameters_0.v"

`timescale 1ns/100ps
module ddr_cntl_a_data_path_0(

     user_input_data,
     user_data_mask,
     clk,                
     clk90,   
     reset,              
     reset90,            
     reset180,           
     reset270,           
     write_enable,       
     rst_dqs_div_in,      
     delay_sel,      
     
    
	dqs_int_delay_in0,

	dqs_int_delay_in1,

	dqs_int_delay_in2,

	dqs_int_delay_in3, 

     dq,                        
     u_data_val,         
     user_output_data,  
     write_en_val,            reset90_r_val,      
     data_mask_f,        
     data_mask_r,        
     write_data_falling,
     write_data_rising);  


   input      [((`data_width*2)-1):0] user_input_data;
   input     [((`data_mask_width*2) -1):0] user_data_mask;
   input      clk;
   input      clk90;
   input      reset;
   input      reset90;
   input      reset180;
   input      reset270;
   input      write_enable;
   input      rst_dqs_div_in;
   input      [4:0] delay_sel;   

	
	input      dqs_int_delay_in0;

	input      dqs_int_delay_in1;

	input      dqs_int_delay_in2;

	input      dqs_int_delay_in3;

   input      [(`data_width-1):0] dq;       
   output     u_data_val;
   output     [((`data_width*2)-1):0] user_output_data;
   output     write_en_val;
   output     reset90_r_val;
   output     [((`data_mask_width)-1):0] data_mask_f;
   output     [((`data_mask_width)-1):0] data_mask_r;
   output     [(`data_width-1):0] write_data_falling;
   output     [(`data_width-1):0] write_data_rising;





   wire  reset_r;
   wire  reset90_r;
   wire  reset90_r1;
   wire  reset180_r;
   wire  reset270_r;                                
   wire  [3:0] fifo0_rd_addr;
   wire  [3:0] fifo1_rd_addr;                          
   wire  read_valid_data_1; 


   wire  [3:0] fifo_00_wr_addr;           
   wire  [3:0] fifo_01_wr_addr;           

   wire  [3:0] fifo_10_wr_addr;           
   wire  [3:0] fifo_11_wr_addr;           

   wire  [3:0] fifo_20_wr_addr;           
   wire  [3:0] fifo_21_wr_addr;           

   wire  [3:0] fifo_30_wr_addr;           
   wire  [3:0] fifo_31_wr_addr;                  

	
   wire  fifo_00_wr_en;
   wire  fifo_01_wr_en;

   wire  fifo_10_wr_en;
   wire  fifo_11_wr_en;

   wire  fifo_20_wr_en;
   wire  fifo_21_wr_en;

   wire  fifo_30_wr_en;
   wire  fifo_31_wr_en;
	





   wire  dqs0_delayed_col0;
   wire  dqs0_delayed_col1;

   wire  dqs1_delayed_col0;
   wire  dqs1_delayed_col1;

   wire  dqs2_delayed_col0;
   wire  dqs2_delayed_col1;

   wire  dqs3_delayed_col0;
   wire  dqs3_delayed_col1;
   


   assign reset90_r_val = reset90_r;

   ddr_cntl_a_data_read_0 data_read0(
            .clk90               (clk90),
            .reset90_r           (reset90_r1),
	    .ddr_dq_in           (dq),
            .read_valid_data_1   (read_valid_data_1),   

	    
	    .fifo_00_wr_en	( fifo_00_wr_en),
	    .fifo_01_wr_en	( fifo_01_wr_en),

	    .fifo_10_wr_en	( fifo_10_wr_en),
	    .fifo_11_wr_en	( fifo_11_wr_en),

	    .fifo_20_wr_en	( fifo_20_wr_en),
	    .fifo_21_wr_en	( fifo_21_wr_en),

	    .fifo_30_wr_en	( fifo_30_wr_en),
	    .fifo_31_wr_en	( fifo_31_wr_en),

	    
            .fifo_00_wr_addr     (fifo_00_wr_addr),
            .fifo_01_wr_addr     (fifo_01_wr_addr),

            .fifo_10_wr_addr     (fifo_10_wr_addr),
            .fifo_11_wr_addr     (fifo_11_wr_addr),

            .fifo_20_wr_addr     (fifo_20_wr_addr),
            .fifo_21_wr_addr     (fifo_21_wr_addr),

            .fifo_30_wr_addr     (fifo_30_wr_addr),
            .fifo_31_wr_addr     (fifo_31_wr_addr),

	    
 	    .dqs0_delayed_col0   (dqs0_delayed_col0),
 	    .dqs0_delayed_col1   (dqs0_delayed_col1),

 	    .dqs1_delayed_col0   (dqs1_delayed_col0),
 	    .dqs1_delayed_col1   (dqs1_delayed_col1),

 	    .dqs2_delayed_col0   (dqs2_delayed_col0),
 	    .dqs2_delayed_col1   (dqs2_delayed_col1),

 	    .dqs3_delayed_col0   (dqs3_delayed_col0),
 	    .dqs3_delayed_col1   (dqs3_delayed_col1),

            .user_output_data    (user_output_data),
            .fifo0_rd_addr_val   (fifo0_rd_addr),
            .fifo1_rd_addr_val   (fifo1_rd_addr )
	    );



    ddr_cntl_a_data_read_controller_0  data_read_controller0(
            .clk90                  (clk90),
            .reset_r                (reset_r),
            .reset90_r              (reset90_r1),
            .rst_dqs_div_in         (rst_dqs_div_in), 
            .delay_sel              (delay_sel),

            
            .dqs_int_delay_in0      (dqs_int_delay_in0),

            .dqs_int_delay_in1      (dqs_int_delay_in1),

            .dqs_int_delay_in2      (dqs_int_delay_in2),

            .dqs_int_delay_in3      (dqs_int_delay_in3),

	    
            .fifo_00_wr_en_val      (fifo_00_wr_en),
            .fifo_01_wr_en_val      (fifo_01_wr_en),

            .fifo_10_wr_en_val      (fifo_10_wr_en),
            .fifo_11_wr_en_val      (fifo_11_wr_en),

            .fifo_20_wr_en_val      (fifo_20_wr_en),
            .fifo_21_wr_en_val      (fifo_21_wr_en),

            .fifo_30_wr_en_val      (fifo_30_wr_en),
            .fifo_31_wr_en_val      (fifo_31_wr_en),

	    
            .fifo_00_wr_addr_val    (fifo_00_wr_addr),
            .fifo_01_wr_addr_val    (fifo_01_wr_addr),

            .fifo_10_wr_addr_val    (fifo_10_wr_addr),
            .fifo_11_wr_addr_val    (fifo_11_wr_addr),

            .fifo_20_wr_addr_val    (fifo_20_wr_addr),
            .fifo_21_wr_addr_val    (fifo_21_wr_addr),

            .fifo_30_wr_addr_val    (fifo_30_wr_addr),
            .fifo_31_wr_addr_val    (fifo_31_wr_addr),

	    
	    .dqs0_delayed_col0_val  (dqs0_delayed_col0),
	    .dqs0_delayed_col1_val  (dqs0_delayed_col1),

	    .dqs1_delayed_col0_val  (dqs1_delayed_col0),
	    .dqs1_delayed_col1_val  (dqs1_delayed_col1),

	    .dqs2_delayed_col0_val  (dqs2_delayed_col0),
	    .dqs2_delayed_col1_val  (dqs2_delayed_col1),

	    .dqs3_delayed_col0_val  (dqs3_delayed_col0),
	    .dqs3_delayed_col1_val  (dqs3_delayed_col1),

            .fifo0_rd_addr          (fifo0_rd_addr),
            .fifo1_rd_addr          (fifo1_rd_addr),
            .u_data_val             (u_data_val),
            .read_valid_data_1_val  (read_valid_data_1)
	    );

         
    ddr_cntl_a_data_write_0 data_write0(
          .user_input_data    (user_input_data),
          .user_data_mask     (user_data_mask),
          .clk90              (clk90),
          .reset90_r          (reset90_r),
          .reset270_r         (reset270_r),
          .write_enable       (write_enable),
          .write_en_val       (write_en_val),
          .write_data_falling (write_data_falling),
          .write_data_rising  (write_data_rising),
          .data_mask_f        (data_mask_f),
          .data_mask_r        (data_mask_r));

   ddr_cntl_a_data_path_rst  data_path_rst0 (
          .clk                (clk),            
          .clk90              (clk90),
          .reset              (reset),
          .reset90            (reset90),
          .reset180           (reset180),
          .reset270           (reset270),
          .reset_r            (reset_r),
          .reset90_r          (reset90_r),
          .reset90_r1         (reset90_r1),
          .reset180_r         (reset180_r),
          .reset270_r         (reset270_r));

endmodule