?? ddr_cntl_a_script_pre_0.tcl
字號(hào):
source ../synth/script_pre1.tcl
add_input_file ddr_cntl_a.sdc
set_hierarchy_separator /
setup_design -manufacturer Xilinx -family {SPARTAN3} -part xc3s4000fg900 -speed -4
setup_design -design ddr_cntl_a
setup_design -2004c_compile_mode
setup_design -encoding=onehot
setup_analysis -num_summary_paths=100
setup_analysis -num_critical_paths=100
compile
create_clock -design rtl -name SYS_CLK infrastructure_top0/lvds_clk_input/O -period 2 -waveform {0 1} -domain ClockDomain2
synthesize
save_impl
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