project -new 
add_file -verilog "../rtl/ddr_cntl_a.v"add_file -verilog "../rtl/ddr_cntl_a_addr_gen_0.v"add_file -verilog "../rtl/ddr_cntl_a_cal_ctl_0.v"add_file -verilog "../rtl/ddr_cntl_a_cal_top.v"add_file -verilog "../rtl/ddr_cntl_a_clk_dcm.v"add_file -verilog "../rtl/ddr_cntl_a_cmd_fsm_0.v"add_file -verilog "../rtl/ddr_cntl_a_cmp_data_0.v"add_file -verilog "../rtl/ddr_cntl_a_controller_0.v"add_file -verilog "../rtl/ddr_cntl_a_controller_iobs_0.v"add_file -verilog "../rtl/ddr_cntl_a_data_path_0.v"add_file -verilog "../rtl/ddr_cntl_a_data_path_iobs_0.v"add_file -verilog "../rtl/ddr_cntl_a_data_path_rst.v"add_file -verilog "../rtl/ddr_cntl_a_data_read_0.v"add_file -verilog "../rtl/ddr_cntl_a_data_read_controller_0.v"add_file -verilog "../rtl/ddr_cntl_a_data_write_0.v"add_file -verilog "../rtl/ddr_cntl_a_ddr1_dm_0.v"add_file -verilog "../rtl/ddr_cntl_a_ddr1_test_bench_0.v"add_file -verilog "../rtl/ddr_cntl_a_dqs_delay.v"add_file -verilog "../rtl/ddr_cntl_a_fifo_0_wr_en_0.v"add_file -verilog "../rtl/ddr_cntl_a_fifo_1_wr_en_0.v"add_file -verilog "../rtl/ddr_cntl_a_glbl.v"add_file -verilog "../rtl/ddr_cntl_a_infrastructure.v"add_file -verilog "../rtl/ddr_cntl_a_infrastructure_iobs_0.v"add_file -verilog "../rtl/ddr_cntl_a_infrastructure_top.v"add_file -verilog "../rtl/ddr_cntl_a_iobs_0.v"add_file -verilog "../rtl/ddr_cntl_a_lfsr32_0.v"add_file -verilog "../rtl/ddr_cntl_a_main_0.v"add_file -verilog "../rtl/ddr_cntl_a_mybufg_0.v"add_file -verilog "../rtl/ddr_cntl_a_parameters_0.v"add_file -verilog "../rtl/ddr_cntl_a_RAM8D_0.v"add_file -verilog "../rtl/ddr_cntl_a_rd_gray_cntr.v"add_file -verilog "../rtl/ddr_cntl_a_s3_ddr_iob.v"add_file -verilog "../rtl/ddr_cntl_a_s3_dqs_iob.v"add_file -verilog "../rtl/ddr_cntl_a_tap_dly_0.v"add_file -verilog "../rtl/ddr_cntl_a_top_0.v"add_file -verilog "../rtl/ddr_cntl_a_wr_gray_cntr.v"
add_file -constraint "../synth/mem_interface_top_synp.sdc"
add_file -constraint "../synth/ddr_cntl_a.sdc"
impl -add rev_1
set_option -technology spartan3
set_option -part xc3s4000
set_option -package fg900
set_option -speed_grade -4
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "ddr_cntl_a"
set_option -frequency 133
set_option -fanout_limit 1000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -fixgatedclocks 0
set_option -retiming 1
set_option -modular 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -write_apr_constraint 1
project -result_file "../synth/rev_1/ddr_cntl_a.edf"
set_option -vlog_std v2001
set_option -auto_constrain_io 0
impl -active "../synth/rev_1"
project -run hdl_info_gen -fileorder
project -run
project -save